參數(shù)資料
型號： P95020ZNQGI8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： QFN-132
文件頁數(shù)： 29/137頁
文件大?。?/td> 3533K
代理商： P95020ZNQGI8
P95020 / Preliminary Datasheet
Revision 0.7.10
124
2010 Integrated Device Technology, Inc.
16.0 LDO MODULE
FEATURES
Four external use LDOs with current output up to 50mA
Initialization and power sequencing controlled by an
external CPU or the Embedded Microcontroller
Output voltage adjustable in 25mV steps from 0.75V
to 3.7V
Programmable Overcurrent / Short Circuit Protection
Three external use LDOs with current output up to
150mA
Initialization and power sequencing controlled by an
external CPU or the Embedded Microcontroller
Output voltage adjustable in 25mV steps from 0.75V
to 3.7V
Programmable Overcurrent / Short Circuit Protection
One user-selectable (3.0V or 3.3V), always-on low-power
LDO
10mA maximum output current
Programmable Over Current / Short Circuit Protection
DESCRIPTION
The P95020 includes two types of LDOs for external use:
normal LDOs (NMLDO) and one low-power, always on
LDO (LPLDO).
There are seven NMLDOs which are
powered by external power inputs.
The LPLDO is
powered by VSYS. All of the external use LDOs share a
common ground pin.
The P95020 also includes LDOs which are used by other
functional blocks within the device. The LDOs used by
the Audio module (LDO_AUDIO_18 and LDO_AUDIO_33)
are powered by a dedicated power input. The remaining
internal-use LDOs are powered by VSYS.
The power-up of each LDO is controlled by a built-in
current-limiter.
After each LDO is enabled, its current-
limiter will be turned-on (~100-200
s) and then the LDO
will ramp up to the configured current-limit setting.
The global enable control and each local enable control
(defined in each local LDO register) are AND-ed together
to enable each specific LDO.
LDO_150_0
DACVOUT: 0x60 [6:0]
DACILIM: 0x61 [1:0]
LDO_150_1
DACVOUT: 0x62 [6:0]
DACILIM: 0x63 [1:0]
LDO_150_2
DACVOUT: 0x64 [6:0]
DACILIM: 0x65 [1:0]
LDO_50_0
DACVOUT: 0x66 [6:0]
DACILIM: 0x67 [1:0]
LDO_50_1
DACVOUT: 0x68 [6:0]
DACILIM: 0x69 [1:0]
LDO_50_2
DACVOUT: 0x6A [6:0]
DACILIM: 0x6B [1:0]
LDO_50_3
DACVOUT: 0x6C [6:0]
DACILIM: 0x6D [1:0]
VDD_AUDIO18
VDD_AUDIO33
VDD_CKGEN33
VDD_CKGEN18
LDO_LP
VOUTSEL33_30
0x72 [0:0]
I2C/I2S
SUB-BLOCK
MICROCONTROLLER
SUB-BLOCK
UPPER BYTE OFFSET: 0xA0
LDO_IN1
LDO_IN2
LDO_150_0
LDO_150_1
LDO_150_2
LDO_50_0
LDO_50_1
LDO_50_2
LDO_50_3
LDO_GND
V
D
_
C
K
G
E
N
3
V
D
_
C
K
G
E
N
1
8
V
D
_
A
U
D
IO
3
L
D
O
_
IN
3
V
S
Y
S
REGISTER BUS
D
G
N
D
GLOBAL POR
A
G
N
D
L
D
O
_
L
P
Internal Sub-Blocks
C
K
G
E
N
_
G
N
D
LDO
EMBUP18
Figure 33
– LDO_050 / LDO_150 Block Diagram
相關(guān)PDF資料
PDF描述
P95020ZLLG 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124
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