參數(shù)資料
型號： P95020ZNQGI8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： QFN-132
文件頁數(shù)： 77/137頁
文件大小： 3533K
代理商： P95020ZNQGI8
P95020 / Preliminary Datasheet
Revision 0.7.10
44
2010 Integrated Device Technology, Inc.
ADC1L_IN_DGAIN = IC Address = Page-1: 180(0xB4), C Address = 0xA1B4
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[3:0]
A1VL
Fh
RW
0h = 22.5 dB gain
Fh = 0 dB gain
Left Digital Input Gain
[6:4]
RESERVED
000b
RW
RESERVED
7
MUTE_L
1b
RW
0 = Not Muted
1 = Muted
Left Mute
ADC1R_IN_DGAIN = IC Address = Page-1: 181(0xB5), C Address = 0xA1B5
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[3:0]
A1VR
Fh
RW
0h = 22.5 dB gain
Fh = 0 dB gain
Right Digital Input Gain
[6:4]
RESERVED
000b
RW
RESERVED
7
MUTE_R
1b
RW
0 = Not Muted
1 = Muted
Right Mute
2.15.14 AUDIO - ADC1 Digital Boost Gain Control Register
This register selects the amount of boost applied after ADC1 but before the ADC1 output gain/AGC.
ADC1_IN_DBOOST = IC Address = Page-1: 182(0xB6), C Address = 0xA1B6, Offset =
0xB6
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[1:0]
DBR
11b
RW
0h = 30 dB Gain
1h = 20 dB Gain
2h = 10 dB Gain
3h = 0 dB Gain
Right Boost
[3:2]
RESERVED
00b
RW
RESERVED
[5:4]
DBL
11b
RW
0h = 30 dB Gain
1h = 20 dB Gain
2h = 10 dB Gain
3h = 0 dB Gain
Left Boost
[7:6]
RESERVED
00b
RW
RESERVED
2.15.15 AUDIO - ADC1 Control Register
This register controls the function of the High pass filter for ADC1
ADC1_CTRL = IC Address = Page-1: 183(0xB7), C Address = 0xA1B7, Offset = 0xB7
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[3:0]
RESERVED
0000b
RW
RESERVED
4
HPF_FREZ
0b
RW
0 = Disabled
1 = Enabled
High-pass filter freeze
5
RESERVED
0b
RW
RESERVED
6
HPF_DIS
0b
RW
0 = Not Disabled
1 = Disabled
High Pass Filter Disable
7
RESERVED
0b
RW
RESERVED
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