參數(shù)資料
型號(hào)： P95020ZLLGI8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124
封裝： LLGA-124
文件頁數(shù)： 60/137頁
文件大?。?/td> 3533K
代理商： P95020ZLLGI8
P95020 / Preliminary Datasheet
Revision 0.7.10
29
2010 Integrated Device Technology, Inc.
Input Volume Controls
DAC0
DAC1
Line Input
Analog Mic (in analog mic mode only.)
Master Volume Control
The analog mixer has 4 input sources. Each input has an independent volume control that provides gain from -34.5 dB to
+12 dB (1.5 dB steps) and mute. After mixing, the output may be attenuated up to 46.5 dB (1.5 dB steps) before being
sent to ADC0, the headphone output port and the line output port.
2.9 AUDIO - DIGITAL AUDIO INPUT/OUTPUT INTERFACE
The Digital Audio Input/ Output Interface consists of:
Dual IS input/output interface with independent bit rate/depth
Each IS input/output pair will operate at same bit rate/depth
MCLK is shared and may be programmed for 64, 128, 256, or 384 times the base rate (44.1 kHz or 48 kHz)
The MCLK is used to align the IS port signals to the host.
PCON Register
– MCLK_CFG: IC Address = Page-0: 55(0x37), C Address = 0xA037
Bit
Bit Name
Default
Settings
User
Type
Value
Description / Comments
[2:0]
MCLK_RATE
000b
RW
Only meaningful when MCLK_SEL bit is set. See
table below.
3
MCLK_DIV2
0b
RW
Only meaningful when MCLK_SEL bit is set. See
table below.
4
MCLK_FROM_I2S
0b
RW
0 = MCLK to audio selected from
GPIO9 pin
1 = MCLK to audio selected from
I2S_BCLK2 pin
5
MCLK_REMAP_EN
0b
RW
0 = MCLK is selected from MCLK I/O
1 = MCLK is selected from I2S or
GPIO9 pin
MCLK I/O does not bond out due to pin-count
constraint
6
RESERVED
0b
RW
RESERVED
7
MCLK_SEL
0b
RW
0 = Audio clock source from 48 MHz
clock from CLKGEN
1 = Audio Clock source from MCLK
MCLK source selection
Table 5 - MCLK Rate selection: MCLK_DIV2: MCLK_RATE
MCLK_DIV2:MCLK_RATE[2:0]
MCLK Input frequency
Comments
00xx
12.288M
0100
11.2896M
0101
18.432M
0110
16.9344
0111
12M
10xx
24.576M
1100
22.5792M
1101
36.864M
1110
33.8688M
1111
24M
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