- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369945 > P90CE201 (NXP Semiconductors N.V.) 16-bit microcontroller PDF資料下載
參數(shù)資料
| 型號： | P90CE201 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 16-bit microcontroller |
| 中文描述： | 16位微控制器 |
| 文件頁數(shù)： | 68/77頁 |
| 文件大?。?/td> | 235K |
| 代理商： | P90CE201 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁當(dāng)前第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁
August 1993
68
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
15.3.4
F
AST
I
2
C-
BUS TIMING
.
Table 58
Fast I
2
C-bus timing.
Notes
1.
A device must internally provide a hold time of at least 300 ns for the SDA signal, referenced to V
IHmin
of the SCL
signal, in order to bridge the undefined region of the falling edge of SCL. The maximum t
HD;DAT
has to be met only if
the device does not stretch the SCL LOW period (t
LOW
).
A fast-mode I
2
C-bus device can be used in a “0-to-100 kbit/s” I
2
C-bus system and then the requirement
t
SU;DAT
> 250 ns must be fulfilled. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. But if such a device stretches the LOW period of the SCL signal, it must output the next data bit
to the SDA line (t
RDmax
+
t
SU;DAT
) = 1000
+
250 = 1250 ns before the SCL line is released according to the existing
“0-to-100 kbit/s” I
2
C-bus specification.
C
b
= Total capacitance value of one bus line in pF.
2.
3.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
f
SCL
t
BUF
t
HD; STA
t
LOW
t
HIGH
t
SU; STA
t
HD; DAT
t
SU; DAT
t
RC
;t
RD
t
FC;
t
FD
t
SU; STO
C
b
SCL clock frequency
bus free time between a STOP and START condition
hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
set-up time (repeated) START
data hold time (note 1)
data set-up time (note 2)
rise time of both SDA and SCL lines (note 3)
fall time of both SDA and SCL lines (note 3)
set-up time for STOP condition
capacitive load of each bus line
0
1300
600
1300
600
600
0
100
(20
+
0.1Cb)
(20
+
0.1Cb)
600
400
900
300
300
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P90CE201AEB | 16-bit microcontroller |
| P9217 | PbS photoconductive detector |
| P930 | CdS photoconductive cell |
| PA025XSB | This technical specification applies to 2.5inch color TFT-LCD panel. |
| PA025XSC | This technical specification applies to 2.5inch color TFT-LCD panel. |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P90CE201AEB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16-bit microcontroller |
| P90CL301 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage 16-bit microcontroller |
| P90CL301BFH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage 16-bit microcontroller |
| P-90-F | 制造商:Hozan Tool Industrial Co Ltd 功能描述: |
| P90PCT101PC | 制造商:PERFORMANCE/ 功能描述:90PCT101PC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。