參數(shù)資料
型號： P90CE201
廠商： NXP Semiconductors N.V.
英文描述： 16-bit microcontroller
中文描述： 16位微控制器
文件頁數(shù)： 24/77頁
文件大?。?/td> 235K
代理商： P90CE201
August 1993
24
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
6.3.2
S
YSTEM
C
ONTROL
R
EGISTER
2 (SYSCON2)
Fig.19 System Control Register 2 (SYSCON2).
handbook, full pagewidth
0
T1
PS
T1
PO
MLB012
1
TOED
0
2
5
4
3
8
7
6
IM WD
9
15
14
13
12
11
10
bit
I C2
CON
I C1
CON
T2
SEL
PSBPCLK
1
PSBPCLK
0
TO
PS
TOED
1
I C1
PO
Table 12
Description of SYSCON2 bits.
SYMBOL
BIT
FUNCTION
SYSCON2.15
to
SYSCON2.13
SYSCON2.12
These three bits are not used.
I
2
C2CON
This bit along with the three bits CR0, CR1 and CR2 held in the Serial Control
Register (S2CON), are used to select the bitrate of the I
2
C-bus 2 interface.
If I
2
C2CON = 0; the interface operates with a high bitrate. If I
2
C2CON = 1; the
interface operates with a low bitrate.
This bit along with the three bits CR0, CR1 and CR2 held in the Serial Control
Register (S1CON), are used to select the bitrate of the I
2
C-bus 1 interface.
If I
2
C1CON = 0; the interface operates with a high bitrate. If I
2
C1CON = 1; the
interface operates with a low bitrate.
This bit selects the frequency of the clock for Timer 2. If T2SEL = 0; the timer
operates at a frequency of f
XTAL
/2. If T2SEL = 1; the timer operates at a frequency
of BPCLK/4.
These two bits control the prescaler for the basic peripheral clock. See Table 13.
I
2
C1CON
SYSCON2.11
T2SEL
SYSCON2.10
PSBPCLK1
PSBPCLK0
IM
SYSCON2.9
SYSCON2.8
SYSCON2.7
If IM = 0; level 7 is loaded into the Status Register during interrupt processing to
prevent the CPU from being interrupted by another interrupt source. If IM = 1; the
current interrupt level is loaded into the Status Register allowing nested interrupts.
This bit enables or disables the Watchdog timer for bus error (internal) detection.
If WD = 0; the timer is disabled. If WD = 1; the timer is enabled for bus error
detection. If no acknowledge has been sent by the addressed device after 128
×
16
internal clock cycles the on-chip bus error signal is activated.
The state of this bit determines whether general port pins GP.7/SDA1 and
GP.6/SCL1 are used as port pins or in their I
2
C-bus function. When I
2
C1P0 = 0; the
port function is selected. When I
2
C1P0 = 1; the I
2
C-bus is selected.
This bit enables or disables the prescaler for Timer 0. If T0PS = 0; the prescaler is
disabled and the timer operates at a frequency of f
XTAL
/2. If T0PS = 1; the prescaler
is enabled and the timer operates at a frequency of f
XTAL
/32.
These two bits select which transition at the external input will trigger an increment
of Timer 0. See Table 14.
WD
SYSCON2.6
I
2
C1PO
SYSCON2.5
T0PS
SYSCON2.4
T0ED1
T0ED0
SYSCON2.3
SYSCON2.2
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