August 1993
32
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
7.2
Instruction timing
This data assumes that both memory read and write cycle times are four internal clock periods (no additional wait states).
Additional wait states for memory accesses have to be added to the total instruction time.
Accesses to registers listed in the Register Map are only three clock periods, therefore one clock period can be
subtracted for each access to such a register. However, access to the UART registers takes up to ten clock periods due
to synchronization. Consequently, ten clock periods have to be added for UART register accesses.
Table 17
Effective address calculation times.
Note
1.
The number of bus read and write cycles are shown in parentheses as (R/W).
Table 18
MOVE Byte and Move Word instruction clock periods.
SOURCE
ADDRESSING MODE
BYTE, WORD
LONG
Rn
(An)
(An)
+
(An)
d(An)
d(An, Xi)
xxx.S
xxx.L
d(PC)
d(PC, Xi)
#xxx
Data Address Register Direct
Address Register Indirect
Address Register Indirect postincrement
Address Register Indirect predecrement
Address Register Indirect Displacement
Address Register Indirect with Index
Absolute Short
Absolute Long
Program Counter with Displacement
Program Counter with Index
Immediate
0
4
4
7
11
14
8
12
11
14
4
(0/0)
(1/0)
(1/0)
(1/0)
(2/0)
(2/0)
(2/0)
(3/0)
(2/0)
(2/0)
(1/0)
0
8
8
11
15
18
12
16
15
18
8
(0/0)
(2/0)
(2/0)
(2/0)
(3/0)
(3/0)
(3/0)
(4/0)
(3/0)
(3/0)
(2/0)
SOURCE
Rn
(An)
(An)
+
(An)
d(An)
d(An,Xi)
xxx.S
xxx.L
Rn
(An)
(An)
+
(An)
d(An)
d(An,Xi)
xxx.S
xxx.L
d(PC)
d(PC,Xi)
#xxx
7
11
11
14
18
21
15
19
18
21
11
(1/0)
(2/0)
(2/0)
(2/0)
(3/0)
(3/0)
(3/0)
(4/0)
(3/0)
(3/0)
(2/0)
11
15
15
18
22
25
19
23
22
25
15
(1/1)
(2/1)
(2/1)
(2/1)
(3/1)
(3/1)
(3/1)
(4/1)
(3/1)
(3/1)
(2/1)
11
15
15
18
22
25
19
23
22
25
15
(1/1)
(2/1)
(2/1)
(2/1)
(3/1)
(3/1)
(3/1)
(4/1)
(3/1)
(3/1)
(2/1)
14
18
18
22
25
28
22
26
25
28
18
(1/1)
(2/1)
(2/1)
(2/1)
(3/1)
(3/1)
(3/1)
(4/1)
(3/1)
(3/1)
(2/1)
18
22
22
25
29
32
26
30
29
32
22
(1/1)
(2/1)
(2/1)
(2/1)
(3/1)
(3/1)
(3/1)
(4/1)
(3/1)
(3/1)
(2/1)
21
25
25
28
32
35
29
33
32
35
25
(1/1)
(2/1)
(2/1)
(2/1)
(3/1)
(3/1)
(3/1)
(4/1)
(3/1)
(3/1)
(2/1)
15
19
19
22
26
29
23
27
26
29
19
(1/1)
(2/1)
(2/1)
(2/1)
(3/1)
(3/1)
(3/1)
(4/1)
(3/1)
(3/1)
(2/1)
19
23
23
26
30
33
27
31
30
33
23
(1/1)
(2/1)
(2/1)
(2/1)
(3/1)
(3/1)
(3/1)
(4/1)
(3/1)
(3/1)
(2/1)