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| 型號： | P90CE201 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 16-bit microcontroller |
| 中文描述： | 16位微控制器 |
| 文件頁數(shù)： | 50/77頁 |
| 文件大?。?/td> | 235K |
| 代理商： | P90CE201 |
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August 1993
50
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
9.3.3
UART I
NTERRUPT REGISTERS
The UART interface contains four registers for the control of the transmitter and receiver interrupts. One pair of registers
(UTIR and UTIV) provide independent control of transmitter interrupts; the other pair of registers (URIR and URIV)
provide independent control of receiver interrupts.
In the following register descriptions “x” can be replaced by “T” for transmitter, or “R” for receiver.
9.3.4
UART T
RANSMITTER
/R
ECEIVER
I
NTERRUPT
R
EGISTER
(U
X
IR)
These registers have a default value of XX0X0000
b
.
Table 44
Description of UxIR bits.
SYMBOL
AVN
BIT
FUNCTION
UxIR.7
UxIR.6
UxIR.5
Reserved
Reserved
Autovector. When AVN = 0; the transmitter/receiver interrupt is an autovectored
interrupt and the processor calculates the appropriate vector from a fixed vector
table. AVN = 0 is also the default value. When AVN = 1; the transmitter/receiver
interrupt is a vectored interrupt and the peripheral must provide an 8-bit vector
number.
Reserved
Pending Interrupt Request. This bit is set to a logic 1 when a valid interrupt request
has been detected. It is automatically reset by the interrupt acknowledge cycle from
the CPU. If PIR = 0; there is no pending interrupt request; this is also the default
value. PIR can be reset by software by writing a logic 0 to this location.
Interrupt Priority Level. These three bits determine the interrupt priority level of the
interrupt requested by the transmitter/receiver. See Table 45.
UxIR.4
UxIR.3
PIR
IPL2
IPL1
IPL0
UxIR.2
UxIR.1
UXIR.0
Fig.33 UART Transmitter/Receiver Interrupt Register (UxIR).
bit 7
bit 6
bit 5
AVN
bit 4
bit 3
PIR
bit 2
IPL2
bit 1
IPL1
bit 0
IPL0
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