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| 型號： | P90CE201 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 16-bit microcontroller |
| 中文描述： | 16位微控制器 |
| 文件頁數(shù)： | 28/77頁 |
| 文件大?。?/td> | 235K |
| 代理商： | P90CE201 |
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August 1993
28
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
7
The P90CE201 is completely code compatible with the 68000. Consequently, programs developed for the 68000 will
run on the P90CE201. This applies to both the source and object codes. The instruction set was designed to minimize
the number of mnemonics that the programmer has to remember.
INSTRUCTION SET
MNEMONIC
DESCRIPTION
OPERATION
CONDITION CODES
X
N
Z
V
C
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ASL, ASR
B
CC
BCHG
Add Decimal with Extend (Destination)
10
+
(Source)
10
+ X
→
Destination
Add Binary
(Destination)
+
(Source)
→
Destination
Add Address
(Destination)
+
(Source)
→
Destination
Add Immediate
(Destination)
+
Immediate Data
→
Destination
Add Quick
(Destination)
+
Immediate Data
→
Destination
Add Extended
(Destination)
+
(Source)
+
X
→
Destination
AND Logical
(Destination)
Λ
(Source)
→
Destination
AND Immediate
(Destination)
Λ
Immediate Data
→
Destination
Arithmetic Shift
(Destination) Shifted by < count >
→
Destination
Branch Conditionally
If CC then PC
+
d
→
PC
Test a Bit and Change
~(< bit number >) of Destination
→
Z
~(< bit number >) of Destination
→
< bit number > of Destination
Test a Bit and Clear
~(< bit number >) of Destination
→
Z
Branch Always
PC
+
d
→
PC
Test a Bit and Set
~(< bit number >) of Destination
→
Z
1
→
< bit number > of Destination
Branch to Subroutine
PC
→
SP @
; PC
+
d
→
PC
Test a Bit
~(< bit number >) of Destination
→
Z
Check Register against
Bounds
Clear an Operand
0
→
Destination
Compare
(Destination)
(Source)
Compare Address
(Destination)
(Source)
Compare Immediate
(Destination)
Immediate Data
Compare Memory
(Destination)
(Source)
Test Condition,
Decrement & Branch
+
d
→
PC
Signed Divide
(Destination) / (Source)
→
Destination
Unsigned Divide
(Destination) / (Source)
→
Destination
*
*
*
*
*
*
U
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
U
*
*
*
*
0
0
*
*
*
*
*
*
0
0
*
BCLR
BRA
BSET
*
*
BSR
BTST
CHK
*
*
U
U
U
If Dn < 0 or Dn > (< source >) then TRAP
CLR
CMP
CMPA
CMPI
CMPM
DB
CC
0
*
*
*
*
1
*
*
*
*
0
*
*
*
*
0
*
*
*
*
If (not CC) then Dn
1
→
Dn; if Dn
≠
1 then PC
DIVS
DIVU
*
*
*
*
*
*
0
0
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