參數(shù)資料
型號(hào)： P90CE201
廠商： NXP Semiconductors N.V.
英文描述： 16-bit microcontroller
中文描述： 16位微控制器
文件頁(yè)數(shù)： 60/77頁(yè)
文件大小： 235K
代理商： P90CE201
August 1993
60
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
13.3.2
T
IMER
I
NTERRUPT
R
EGISTER
(TnIR)
Each Timer contains a register for the control of interrupts.
Table 51
Description of TnIR bits.
Table 52
Selection of interrupt priority level.
SYMBOL
AVN
BIT
FUNCTION
TnIR.7
TnIR.6
TnIR.5
Reserved
Reserved
Autovector. When AVN = 0; the timer interrupt is an autovectored interrupt and the
processor calculates the appropriate vector from a fixed vector table. AVN = 0 is
also the default value. When AVN = 1; the timer interrupt is a vectored interrupt
and the peripheral must provide an 8-bit vectored interrupt.
Reserved
Pending Interrupt Request. This bit is set to a logic 1 when a valid interrupt
request has been detected. It is automatically reset by the interrupt acknowledge
cycle from the CPU. If PIR = 0, there is no pending interrupt request; this is also
the default value. The PIR bit can be reset by software by writing a logic 0 to this
location.
Interrupt Priority Level. These three bits determine the interrupt priority level of the
interrupt requested by the timer. See Table 52.
TnIR.4
TnIR.3
PIR
IPL2
IPL1
IPL0
TnIR.2
TnIR.1
TnIR.0
IPL2
IPL1
IPL0
PRIORITY LEVEL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt inhibited; this is also the default value.
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Fig.44 Timer Interrupt Register (TnIR).
bit 7
bit 6
bit 5
AVN
bit 4
bit 3
PIR
bit 2
IPL2
bit 1
IPL1
bit 0
IPL0
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