參數(shù)資料
型號(hào): P89V51RB2FA,529
廠商: NXP Semiconductors
文件頁數(shù): 71/80頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 16K 44-PLCC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 156
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱: 568-2427-5
935278706529
P89V51RB2FA-S
2009-2011 Microchip Technology Inc.
DS39960D-page 73
PIC18F87K22 FAMILY
5.0
RESET
The PIC18F87K22 family of devices differentiates
between various kinds of Reset:
a)
Power-on Reset (POR)
b)
MCLR Reset during normal operation
c)
MCLR Reset during power-managed modes
d)
Watchdog Timer (WDT) Reset (during
execution)
e)
Configuration Mismatch (CM) Reset
f)
Brown-out Reset (BOR)
g)
RESET
Instruction
h)
Stack Full Reset
i)
Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
WDT Resets are covered in Section 28.2 “Watchdog
.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 5-1.
5.1
RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event.
The state of these flag bits, taken together, can be read
to indicate the type of Reset that just occurred. This is
described in more detail in Section 5.7 “Reset State
.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR
VDD
WDT
Time-out
VDD Rise
Detect
PWRT
LF-INTOSC
POR Pulse
Chip_Reset
Brown-out
Reset
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
32
s
PWRT
11-Bit Ripple Counter
66 ms
S
R
Q
Configuration Word Mismatch
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