參數(shù)資料
型號(hào): P89V51RB2FA,529
廠商: NXP Semiconductors
文件頁(yè)數(shù): 64/80頁(yè)
文件大小: 0K
描述: IC 80C51 MCU FLASH 16K 44-PLCC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 156
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 706 (CN2011-ZH PDF)
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱: 568-2427-5
935278706529
P89V51RB2FA-S
2009-2011 Microchip Technology Inc.
DS39960D-page 67
PIC18F87K22 FAMILY
REGISTER 4-3:
PMD1: PERIPHERAL MODULE DISABLE REGISTER 1
R/W-0
PSPMD
CTMUMD
RTCCMD(1)
TMR4MD
TMR3MD
TMR2MD
TMR1MD
EMBMD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PSPMD:
Peripheral Module Disable (PMD) PSP Enable/Disable bit
1
= PMD is enabled for PSP, disabling all of its clock sources
0
= PMD is disabled for PSP
bit 6
CTMUMD:
PMD CTMU Enable/Disable bit
1
= PMD is enabled for CTMU, disabling all of its clock sources
0
= PMD is disabled for CTMU
bit 5
RTCCMD:
PMD RTCC Enable/Disable bit(1)
1
= PMD is enabled for RTCC, disabling all of its clock sources
0
= PMD is disabled for RTCC
bit 4
TMR4MD:
TMR4MD Disable bit
1
= PMD is enabled and all TMR4MD clock sources are disabled
0
= PMD is disabled and TMR4MD is enabled
bit 3
TMR3MD:
TMR3MD Disable bit
1
= PMD is enabled and all TMR3MD clock sources are disabled
0
= PMD is disabled and TMR3MD is enabled
bit 2
TMR2MD:
TMR2MD Disable bit
1
= PMD is enabled and all TMR2MD clock sources are disabled
0
= PMD is disabled and TMR2MD is enabled
bit 1
TMR1MD:
TMR1MD Disable bit
1
= PMD is enabled and all TMR1MD clock sources are disabled
0
= PMD is disabled and TMR1MD is enabled
bit 0
EMBMD:
PMD EMB Enable/Disable bit
1
= PMD is enabled for EMB, disabling all of its clock sources
0
= PMD is disabled for EMB
Note 1:
RTCCMD can only be set to ‘1’ after an EECON2 unlock sequence. Refer to Section 18.0 “Real-Time
for the unlock sequence (Example 18-1).
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