參數(shù)資料
型號: P89C738
廠商: NXP Semiconductors N.V.
英文描述: 8-bit Flash microcontrollers
中文描述: 8位閃存微控制器
文件頁數(shù): 51/64頁
文件大?。?/td> 360K
代理商: P89C738
1998 Apr 07
51
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
Notes
1.
The operating supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 5 ns;
V
IL
= V
SS
+ 0.5 V; V
IH
= V
DD
0.5 V; XTAL2 not connected; EA = RST = Port 0 = V
DD
; the Watchdog Timer is
disabled (by the external reset).
I
DD(max)
at other frequencies can be derived from Fig.28.
The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 5 ns;
V
IL
= V
SS
+0.5 V; V
IH
= V
DD
0.5 V; XTAL2 not connected; the Watchdog Timer is disabled; EA = RST = V
SS
;
Port 0 = P1.6 = P1.7 = V
DD
.
The Power-down current is measured with all output pins disconnected; XTAL2 not connected; Watchdog Timer is
disabled; EA = RST = XTAL1 = V
SS
; Port 0 = P1.6 = P1.7 = V
DD
.
Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW-level
output voltage of ALE, Port 1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0
and Port 2 pins when these pins make a HIGH-to-LOW transition during bus operations. In the worst cases
(capacitive loading
>
100 pF) the noise pulse on the ALE line may exceed 0.8 V. In such cases it may be desirable
to provide ALE with a Schmitt trigger, or use an address latch with a Schmitt trigger STROBE input.
Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
a) Maximum I
OL
per port pin: 10 mA.
b) Maximum I
OL
per 8-bit port: Port 0 = 26 mA; Ports 1, 2, 3, 4 and 5 = 15 mA.
c) Maximum total I
OL
for all output pins: 71 mA.
d) If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current
greater than the listed test conditions.
Capacitive loading on Port 0 and Port 2 may cause the HIGH-level output voltage on ALE and PSEN to momentarily
fall below the 0.9V
DD
specification when the address bits are stabilizing.
2.
3.
4.
5.
6.
7.
V
OH1
HIGH level output voltage
Port 0 in external bus mode,
ALE, PSEN and RST
I
OH
=
800
μ
A; V
DD
= 5 V
±
10%
I
OH
=
300
μ
A
I
OH
=
80
μ
A; note 7
2.4
0.75V
DD
0.9V
DD
40
100
10
V
V
V
k
pF
R
RST
C
I/O
RST pull
down resistor
capacitance of input buffer
test frequency = 1 MHz;
T
amb
= 25
°
C
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
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