1998 Apr 07
30
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
13.4
Status of external pins
Table 20
Status of the external pins during Idle and Power-down modes
13.5
Power Control Register (PCON)
Special modes are activated by software via the SFR PCON. PCON is not bit addressable. The reset value of PCON is
00H.
Table 21
Power Control Register (SFR address 87H)
Table 22
Description of PCON bits
Note
1.
If logic 1s are written to PD and IDL at the same time, PD takes precedence.
MODE
MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
Idle
internal
external
internal
external
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
port data
floating
port data
floating
port data
port data
port data
port data
port data
address
port data
port data
port data
port data
port data
port data
port data
port data
port data
port data
port data
port data
port data
port data
Power-down
7
6
5
4
3
2
1
0
SMOD
ARE
RFI
WLE
GF1
GF0
PD
IDL
BIT
SYMBOL
DESCRIPTION
7
SMOD
Double baud rate bit
. When set to a logic 1 the baud rate is doubled when Timer 1 is
used to generate baud rate, and the Serial Port is used in Modes 1, 2 or 3.
AUX-RAM enable bit.
When set to a logic 1 the AUX-RAM is disabled, so that all
MOVX-instructions access the external data memory.
Reduced Radio Frequency Interference bit
. When set to a logic 1 the toggling of the
ALE pin is prohibited. This bit is cleared on reset. See also Chapters 1 “Features”: on
EMC and 6 “Pinning information”: note 2.
Watchdog Load Enable
. This flag must be set by software prior to loading the
Watchdog Timer (T3). It is cleared when timer T3 is loaded.
General-purpose flag bit
.
6
ARE
5
RFI
4
WLE
3
2
1
0
GF1
GF0
PD
(1)
IDL
(1)
Power-down select.
Setting this bit activates the Power-down mode.
Idle mode select.
Setting this bit activates the Idle mode.