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參數(shù)資料
| 型號： | P89C738 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit Flash microcontrollers |
| 中文描述： | 8位閃存微控制器 |
| 文件頁數(shù)： | 12/64頁 |
| 文件大?。?/td> | 360K |
| 代理商： | P89C738 |
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1
1
P
P
8
P
P2.0/A8 to
P2.2/A10
P2.3/A11 to
P2.4/A12
P2.5/A13 to
P2.7/A15
PSEN
54 to 56
44 to 46
38 to 34
24 to 31
21 to 28
Port 2: P2.0 to P2.7
; 8-bit quasi-bidirectional I/O Port with internal
pull-ups. Port 2 can sink/source one TTL (= 4 LSTTL) input. It can
drive CMOS inputs without external pull-ups.
Port 2 alternative functions are:
A8 to A15
; during access to
external memories (RAM/ROM) that use 16-bit addresses (MOVX
@DPTR) Port 2 emits the high-order address byte (A8 to A15).
Program Store Enable output
: read strobe to the external program
memory via Port 0 and Port 2. It is activated twice each machine
cycle during fetches from external program memory.
When executing out of external program memory two activations of
PSEN are skipped during each access to external data memory.
PSEN is not activated (remains HIGH) during no fetches from
external program memory. PSEN can sink/source 8 LSTTL inputs. It
can drive CMOS inputs without external pull-ups.
Address Latch Enable output
: latches the lower byte of the
address during access to external memory in normal operation. It is
activated every six oscillator periods except during an external data
memory access. ALE can sink/source 8 LSTTL inputs. It can drive
CMOS inputs without an external pull-up.
58 to 59
48 to 49
61, 64
and 65
67
51, 54
and 55
56
23 to 25
26
32
29
ALE/WE
(2)
68
57
27
33
30
WE
: Write Enable.
External Access input
: when during reset, EA is held at a TTL
HIGH level, the CPU executes from the internal program ROM.
When EA is held at a TTL LOW level during reset, the CPU executes
out of external program memory via Port 0 and Port 2. EA is not
allowed to float. EA is latched during reset and don’t care after reset.
EA/V
PP
2
59
29
35
31
V
PP
: programming supply voltage.
Port 0: P0.7 to P0.0
; 8-bit open-drain bidirectional I/O port. It is also
the multiplexed low-order address and data bus during accesses to
external memory:
AD0 to AD7
. During these accesses internal
pull-ups are activated. Port 0 can sink/source 8 LSTTL inputs.
P0.7/AD7 to
P0.4/AD4
P0.3/AD3 to
P0.2/AD2
P0.1/AD1 to
P0.0/AD0
V
DD
3, 5, 6
and 9
11 to 12
60, 61, 62
and 1
3 to 4
30 to 33
36 to 43
32 to 39
22 to 21
14 to 15
6 to 7
20 to 19
17
9
18
44
40
Power supply (+5 V)
pin for normal operation, Idle mode and
Power-down mode.
SYMBOL
PIN
(1)
DESCRIPTION
PLCC68
QFP64
PLCC44
QFP44
DIP40
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P89C739ABA | 8-bit Flash microcontrollers |
| P89C739ABB | 8-bit Flash microcontrollers |
| P89C738ABA | 8-bit Flash microcontrollers |
| P89C738ABB | 8-bit Flash microcontrollers |
| P89C738ABP | 8-bit Flash microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P89C738ABA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit Flash microcontrollers |
| P89C738ABB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit Flash microcontrollers |
| P89C738ABP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit Flash microcontrollers |
| P89C738BBB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| P89C739 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit Flash microcontrollers |
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