參數(shù)資料
型號(hào): P89C738
廠商: NXP Semiconductors N.V.
英文描述: 8-bit Flash microcontrollers
中文描述: 8位閃存微控制器
文件頁(yè)數(shù): 33/64頁(yè)
文件大?。?/td> 360K
代理商: P89C738
1998 Apr 07
33
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
16 MULTIPLE PROGRAMMING ROM (MTP-ROM)
16.1
Features
64 kbytes electrically erasable internal program memory
Up to 64 kbytes external program memory if the internal
program memory is switched off (EA = 0)
Programming and erasing voltage 12 V
±
5%
Command register architecture
– Byte Programming (10
μ
s typical)
– Auto chip erase: 5 seconds (typical; including
pre-programming time)
Auto-erase and auto-program
– DATA polling
– Toggle bit
Minimum 100 erase/program cycles
Advanced CMOS MTP memory technology.
16.2
General description
The P89C738’s MTP memories augment EPROM
functionality with in-circuit electrical erasure and
programming. The P89C738 uses a command register to
manage this functionality.
P89C738’s MTP reliably stores memory contents even
after 100 erase and program cycles. The cell is designed
to optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and
programming operations produces reliable cycling.
The P89C738 uses a V
PP
= 12.0 V
±
5% supply to perform
the auto-erase and auto-program algorithms.
16.3
Automatic programming and Automatic chip
erase
The P89C738 is byte programmable using the Automatic
programming algorithm. The Automatic programming
algorithm does not require the system to time out or verify
the data programmed. At typical room temperature the
chip programming time of the P89C738 is less than
5 seconds.
The device may be erased using the Automatic erase
algorithm. The Automatic erase algorithm automatically
programs the entire array prior to electrical erase.
The timing and verification of the electrical erase are
controlled internally by the device.
16.3.1
A
UTOMATIC PROGRAMMING ALGORITHM
The P89C738 Automatic programming algorithm requires
the user to only write a program set-up command and a
program command (program data and address).
The device automatically times the programming pulse
width, provides the program verification, and counts the
number of sequences. A status bit similar to DATA polling
and a status bit toggling between consecutive read cycles,
provide feedback to the user as to the status of the
programming operation.
16.3.2
A
UTOMATIC ERASE ALGORITHM
The P89C738 Automatic erase algorithm requires the user
to only write an erase set-up command and erase
command. The device will automatically pre-program and
verify the entire array. Then the device automatically times
the erase pulse width, provides the erase verify, and
counts the number of sequences. A status bit similar to
DATA polling and a status bit toggling between
consecutive read cycles, provide feedback to the user as
to the status of the erase operation.
Commands are written to the command register. Register
contents serve as inputs to an internal state-machine
which controls the erase and programming circuitry.
During write cycles, the command register internally
latches address and data needed for the programming and
erase operations. For system design simplification, the
P89C738 is designed to support either WE or CE
controlled writes. During a system write cycle, addresses
are latched on the falling edge of WE or CE whichever
occurs last. Data is latched on the rising edge of WE or CE
whichever occur first. To simplify the following discussion,
theWE pin is used as the write cycle control pin throughout
the rest of this text. All set-up and hold times are with
respect to the WE signal.
16.4
Command definitions
When a low voltage is applied to the V
PP
pin, the contents
of the command register is set to a default value: 00H.
Applying high voltage to the V
PP
pin enables read/write
operations. Device operations are selected by writing
specific data patterns into the command register.
Table 23 defines these P89C738 register commands.
Table 24 defines the bus operations of the P89C738.
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