參數(shù)資料
型號: P89C738
廠商: NXP Semiconductors N.V.
英文描述: 8-bit Flash microcontrollers
中文描述: 8位閃存微控制器
文件頁數(shù): 21/64頁
文件大?。?/td> 360K
代理商: P89C738
1998 Apr 07
21
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
10.2
Timer 2
Timer 2 is functionally similar to the Timer 2 of the 8052AH. Timer 2 is a 16-bit timer/counter which is formed by two
SFRs, TL2 and TH2. Another pair of SFRs, RCAP2L and RCAP2H, form a 16-bit capture register or a 16-bit reload
register.
Like Timer 0 and Timer 1, Timer 2 can operate either as timer or as event counter. This is selected by bit C/T2 in SFR
T2CON. The timer has three operating modes: ‘capture’, ‘a(chǎn)utoload’ and ‘baud rate generator’, which are selected by bits
in SFR T2CON (see Tables 14 and 15).
10.2.1
T
IMER
/C
OUNTER
2 C
ONTROL
R
EGISTER
(T2CON)
Table 14
Timer/Counter 2 Control Register (SFR address C8H)
Table 15
Description of T2CON bits
Table 16
Timer 2 operating modes
X = don’t care.
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
BIT
SYMBOL
DESCRIPTION
7
TF2
Timer 2 overflow flag
. Set by a Timer 2 overflow and must be cleared by software. TF2
will not be set when either RCLK = 1 or TCLK = 1. When Timer 2 interrupt is enabled,
TF2 = 1 will cause the CPU to vector to Timer 2 interrupt routine.
Timer 2 external flag.
Set when either a capture or reload is caused by a negative
transition on T2EX and when EXEN2 = 1. When Timer T2 interrupt is enabled,
EXF2 = 1 will cause the CPU to vector to Timer 2 interrupt routine.
Receive clock flag.
When set, causes the Serial Port to use Timer 2 overflow pulses
for its receive clock in Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used
for the receive clock.
Transmit clock flag.
When set, causes the Serial Port to use Timer 2 overflow pulses
for its transmit clock in Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used
for the transmit clock.
Timer 2 external enable flag
. When set, allows a capture or reload to occur as a result
of a negative transition on T2EX, if Timer 2 is not being used to clock the Serial Port.
EXEN2 = 0, causes Timer 2 to ignore events at T2EX.
Timer 2 start/stop control
. TR2 = 1 starts Timer 2; TR2 = 0 stops Timer 2.
Timer 2 timer or counter select
. C/T2 = 0 selects the internal timer with a clock
frequency of
1
12
f
clk
. C/T2 = 1 selects the external event counter; falling edge triggered.
Capture/reload flag.
When set, capture will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, reloads will occur upon either Timer 2 overflows or negative
transitions at T2EX if EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored
and the timer is forced to reload upon overflow.
6
EXF2
5
RCLK
4
TCLK
3
EXEN2
2
1
TR2
C/T2
0
CP/RL2
RCLK
TCLK
CP/RL2
TR2
MODE
0
0
1
X
0
0
1
X
0
1
X
X
1
1
1
0
16-bit automatic reload
16-bit capture
baud rate generator
off
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