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參數(shù)資料
| 型號： | P28F001BX-T70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 中文描述： | 128K X 8 FLASH 12V PROM, 70 ns, PDIP32 |
| 封裝： | 0.620 X 1.640 INCH, PLASTIC, DIP-32 |
| 文件頁數(shù)： | 2/33頁 |
| 文件大?。?/td> | 436K |
| 代理商： | P28F001BX-T70 |
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28F001BX-T/28F001BX-B
290406–1
Figure 1. 28F001BX Block Diagram
Table 1. Pin Description
Symbol
Type
Name and Function
A
0
–A
16
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally latched during
a write cycle.
DQ
0
–DQ
7
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS:
Inputs data and commands during memory write
cycles; outputs data during memory, Status Register and Identifier read cycles. The
data pins are active high and float to tri-state off when the chip is deselected or the
outputs are disabled. Data is internally latched during a write cycle.
CE
Y
INPUT
CHIP ENABLE:
Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CE
Y
is active low; CE
Y
high deselects the memory device and
reduces power consumption to standby levels.
RP
Y
INPUT
POWERDOWN:
Puts the device in deep powerdown mode. RP
Y
is active low;
RP
Y
high gates normal operation. RP
Y
e
V
HH
allows programming of the boot
block. RP
Y
also locks out erase or write operations when active low, providing data
protection during power transitions. RP
Y
active resets internal automation. Exit
from deep powerdown sets device to Read Array mode.
OE
Y
INPUT
OUTPUT ENABLE:
Gates the device’s outputs through the data buffers during a
read cycle. OE
Y
is active low. OE
Y
e
V
HH
(pulsed) allows programming of the
boot block.
WE
Y
INPUT
WRITE ENABLE:
Controls writes to the Command Register and array blocks. WE
Y
is active low. Addresses and data are latched on the rising edge of the WE
Y
pulse.
V
PP
ERASE/PROGRAM POWER SUPPLY
for erasing blocks of the array or
programming bytes of each block. Note: With V
PP
k
V
PPL
max, memory contents
cannot be altered.
V
CC
DEVICE POWER SUPPLY:
(5V
g
10%)
GND
GROUND
2
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