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參數(shù)資料
| 型號： | P28F001BX-T70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 中文描述： | 128K X 8 FLASH 12V PROM, 70 ns, PDIP32 |
| 封裝： | 0.620 X 1.640 INCH, PLASTIC, DIP-32 |
| 文件頁數(shù)： | 11/33頁 |
| 文件大?。?/td> | 436K |
| 代理商： | P28F001BX-T70 |
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28F001BX-T/28F001BX-B
Program Setup/Program Commands
Programming is executed by a two-write sequence.
The program Setup command (40H) is written to the
Command Register, followed by a second write
specifying the address and data (latched on the ris-
ing edge of WE
Y
) to be programmed. The WSM
then takes over, controlling the program and verify
algorithms internally. After the two-command pro-
gram sequence is written to it, the 28F001BX auto-
matically outputs Status Register data when read
(see Figure 9; Byte Program Flowchart). The CPU
can detect the completion of the program event by
analyzing the WSM Status bit of the Status Register.
Only the Read Status Register command is valid
while programming is active.
When the Status Register indicates that program-
ming is complete, the Program Status bit should be
checked. If program error is detected, the Status
Register should be cleared. The internal WSM verify
only detects errors for ‘‘1s’’ that do not successfully
program to ‘‘0s’’. The Command Register remains in
Read Status Register mode until further commands
are issued to it. If byte program is attempted while
V
PP
e
V
PPL
, the V
PP
Status bit will be set to ‘‘1’’.
Program attempts while V
PPL
k
V
PP
k
V
PPH
pro-
duce spurious results and should not be attempted.
EXTENDED ERASE/PROGRAM
CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some sup-
pliers have implemented redundancy schemes, re-
ducing cycling failures to insignificant levels. Howev-
er, redundancy requires that cell size be doubled; an
expensive solution.
Intel has designed extended cycling capability into
its ETOX flash memory technology. Resulting im-
provements in cycling reliability come without in-
creasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carry-
ing ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electrical field is one-
tenth that of common EEPROMs, minimizing the
probability of oxide defects in the region. Finally, the
peak electric field during erasure is approximately 2
Mv/cm lower than EEPROM. The lower electric field
greatly reduces oxide stress and the probability of
failure.
The 28F001BX-B and 28F001BX-T are capable of
100,000 program/erase cycles on each parameter
block, main block and boot block.
ON-CHIP PROGRAMMING
ALGORITHM
The 28F001BX integrates the Quick Pulse program-
ming algorithm of prior Intel Flash Memory devices
on-chip, using the Command Register, Status Regis-
ter and Write State Machine (WSM). On-chip inte-
gration dramatically simplifies system software and
provides processor-like interface timings to the
Command and Status Registers. WSM operation, in-
ternal program verify and V
PP
high voltage presence
are monitored and reported via appropriate Status
Register bits. Figure 9 shows a system software
flowchart for device programming. The entire se-
quence is performed with V
PP
at V
PPH
. Program
abort occurs when RP
Y
transitions to V
IL
, or V
PP
drops to V
PPL
. Although the WSM is halted, byte
data is partially programmed at the location where
programming was aborted. Block erasure or a re-
peat of byte programming will initialize this data to a
known value.
ON-CHIP ERASE ALGORITHM
As above, the Quick Erase algorithm of prior Intel
Flash Memory devices is now implemented internal-
ly, including all preconditioning of block data. WSM
operation, erase success and V
PP
high voltage pres-
ence are monitored and reported through the Status
Register. Additionally, if a command other than
Erase Confirm is written to the device after Erase
Setup has been written, both the Erase Status and
Program Status bits will be set to ‘‘1’’. When issuing
the Erase Setup and Erase Confirm commands, they
should be written to an address within the address
range of the block to be erased. Figure 10 shows a
system software flowchart for block erase.
Erase typically takes 1–4 seconds per block. The
Erase Suspend/Erase Resume command sequence
allows interrupt of this erase operation to read data
from a block other than that in which erase is
being performed
. A system software flowchart is
shown in Figure 11.
The entire sequence is performed with V
PP
at V
PPH
.
Abort occurs when RP
Y
transitions to V
IL
or V
PP
falls to V
PPL
, while erase is in progress. Block data is
partially erased by this operation, and a repeat of
erase is required to obtain a fully erased block.
11
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