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參數(shù)資料
| 型號： | NT7501H-BDT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 33 X 100 RAM-Map LCD Controller/Driver |
| 中文描述： | 33 × 100 RAM的地圖LCD控制器/驅(qū)動器 |
| 文件頁數(shù)： | 7/38頁 |
| 文件大?。?/td> | 319K |
| 代理商： | NT7501H-BDT |
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NT7501
7
Functional Description
Microprocessor Interface
Interface type selection
The NT7501 can transfer data via 8-bit bi-directional data bus (D7 to D0) or via serial data input (SI). When high or low is
selected for the parity of the P/S pad, either 8-bit parallel data input or serial data input can be selected as shown in Table 1.
When serial data input is selected, the RAM data cannot be read out.
Table 1.
P/S
Type
1
CS
CS2
A0
RD
WR
C86
D7
D6
D0 to D5
H
Parallel Input
1
CS
CS2
A0
RD
WR
C86
D7
D6
D0 to D5
L
Serial Input
1
CS
CS2
A0
-
-
-
SI
SCL
(HZ)
“-” must always be high or low
Parallel Input
When the NT7501 selects parallel input (P/S = high), the 8080 series microprocessor or 6800 series microprocessor can be
selected by causing the C86 pad to go high or low as shown in Table 2.
Table 2.
C86
Type
1
CS
CS2
A0
RD
WR
D0 to D7
H
6800 microprocessor bus
1
CS
CS2
A0
E
W
R
D0 to D7
L
8080 microprocessor bus
1
CS
CS2
A0
RD
RW
D0 to D7
Data Bus Signals
The NT7501 identifies the data bus signal according to A0, E,
W
R
(RD, WR ) signals.
Table 3.
Common
6800 processor
8080 processor
A0
(
W
R
)
RD
WR
Function
1
1
0
1
Reads display data
1
0
1
0
Writes display data
0
1
0
1
Reads status
0
0
1
0
Writes control data in internal register. (Command)
Serial Interface (P/S is low)
The serial interface consists of an 8-bit shift register and a 3-bit counter. The serial data input and serial clock input are enabled
when
1
CS is low and CS2 is high (in chip select status). When the chip is not selected, the shift register and counter are reset.
The serial data of D7, D6,
D0 are read at D7 in this sequence when the serial clock (SCL) goes high. They are converted into
8-bit parallel data and processed on rising edge of every eighth serial clock signal.
The serial data input (SI) is determined to be the display data when A0 is high, and the control data when A0 is low. A0 is read
on the rising edge of every eighth clock signal.
Figure1 shows a timing chart of serial interface signals. The serial clock sign must be terminated correctly against termination
reflection and ambient noise. Operation checkout on the actual machine is recommended.
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