參數(shù)資料
型號(hào)： NT7501H-BDT
廠商： Electronic Theatre Controls, Inc.
英文描述： 33 X 100 RAM-Map LCD Controller/Driver
中文描述： 33 × 100 RAM的地圖LCD控制器/驅(qū)動(dòng)器
文件頁數(shù)： 5/38頁
文件大?。?/td> 319K
代理商： NT7501H-BDT
NT7501
5
System Bus Connection Terminals
Pad No.
Symbol
I/O
Description
27 - 34
D0 - D7
(SI)
(SCL)
I/O
This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit
standard MPU data bus.
When the serial interface is selected (P/S = “L”), then D7 serves as the
serial data input terminal (SI) and D6 serves as the serial clock input
terminal (SCL). At this time, D0 to D5 are set to high impedance.
When the chip select is inactive, D0 to D7 are set to high impedance.
This is connected to the least significant bit of the normal MPU address
bus, and it determines whether the data bits are data or a command.
A0 = “H”: Indicate that D0 to D7 are display data.
A0 = “L”: Indicates that D0 to D7 are control data.
16
A0
I
8
RES
I
When RES is set to “L”, the settings are initialized.
The reset operation is performed by the RES signal level.
11 - 13
1
CS CS2
I
This is the chip select signal. When
chip select becomes active and data/command I/O are enabled
1
CS = “L” and CS2 = “H”, then the
18
RD
(E)
I
When connected to an 8080 MPU, it is active LOW. This pad is
connected to the RD signal of the 8080MPU, and the NT7501 data bus
is in an output statue when this signal is “L”.
When connected to a 6800 Series MPU, this is active HIGH. This is
used as an enable clock input of the 6800 series MPU.
17
WR
R
(
W
)
I
When connected to an 8080 MPU, this is active LOW. This terminal
connects to the 8080 MPU WR signal . The signals on the data bus are
latched at the rising edge of the WR signal.
When connected to a 6800 Series MPU: This is the read/write control
signal input terminal.
When
W
R
= “H”: Read.
When
W
R
= “L”: Write.
14
C86
I
This is the MPU interface switch terminal.
C86 = “H”: 6800 Series MPU interface.
C86 = “L”: 8080 Series MPU interface.
10
P/S
I
This is the parallel data input/serial data input switch terminal.
P/S = “H”: Parallel data input.
P/S = “L”: Serial data input.
The following applies depending on the P/S status:
P/S
"H"
"L"
Data/Command
A0
A0
Data
D0 to D7
SI (D7)
Read/Write
Serial Clock
Write only
SCL (D6)
RDWR
When P/S = “L”, D0 to D5 are HZ. D0 to D5 may be “H”, “L” or Open.
RD(E) and WR (
W
/
R
) are fixed to either “H” or “L”. With serial data
input, RAM display data reading is not supported.
7
M/S
I
This terminal selects the master/slave operation for the NT7501 chips.
Master operation outputs the timing signals that are required for the
LCD display, while slave operation inputs the timing signals required for
the liquid crystal display, synchronizing the liquid crystal display system.
4
CL
I/O
This is the display clock input terminal. When the NT7501 chips are
used in master/slave mode, the various CL terminals must be
connected.
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