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參數(shù)資料
| 型號： | NSC800V |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NSC800TM High-Performance Low-Power CMOS Microprocessor |
| 中文描述： | NSC800TM高性能低功耗CMOS微處理器 |
| 文件頁數(shù)： | 53/76頁 |
| 文件大?。?/td> | 785K |
| 代理商： | NSC800V |
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12.12 Input/Output
(Continued)
OUT
(n), A
Output the Accumulator to the I/O device at address n.
(n)
w
A
7
6
5
4
3
2
1
0
No flags affected
1
1
0
1
0
0
1
1
n
Timing:
M cycles D 3
T states D 11 (4, 3, 4)
Addressing Mode:
Source D Register
Destination D Direct
OUTD
Data is output from memory location (HL) to the I/O device
at port address (C), and the HL memory pointer and byte
counter B are decremented.
(C)
w
(HL)
S: Undefined
B
w
B
b
1
Z: Set if B
b
1
e
0, otherwise reset
HL
w
HL
b
1
H: Undefined
P/V: Undefined
N: Set
C: N/A
0
7
6
5
4
3
2
1
1
1
1
0
1
1
0
1
1
0
1
0
1
0
1
1
Timing:
M cycles D 4
T states D 16 (4, 5, 3, 4)
Addressing Mode:
Implied/Source D Register In-
direct
Destination D Register Indirect
INIR
Data is input from the I/O device at port address (C) to
memory location (HL), the HL memory pointer is increment-
ed, and the byte counter B is decremented. The cycle is
repeated until B
e
0.
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
(HL)
w
(C)
S: Undefined
HL
w
HL
a
1
Z: Set
B
w
B
b
1
H: Undefined
Repeat until B
e
0
P/V: Undefined
N: Set
C: N/A
7
6
5
4
3
2
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
Timing:
For B
i
0
M cycles D 5
T states D 21 (4, 5, 3, 4, 5)
For B
e
0
M cycles D 4
T states D 16 (4, 5, 3, 4)
Addressing Mode:
Implied/Source D Register In-
direct
Destination D Register Indirect
(Note that at the end of each data transfer cycle, interrupts
may be recognized and two refresh cycles will be per-
formed.)
OTIR
Data is output to the I/O device at port address (C) from
memory location (HL), the HL memory pointer is increment-
ed, and the byte counter B is decremented. The cycles are
repeated until B
e
0.
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
(C)
w
(HL)
S: Undefined
HL
w
HL
a
1
H: Undefined
B
w
B
b
1
Z: Set
Repeat until B
e
0
P/V: Undefined
N: Set
C: N/A
0
7
6
5
4
3
2
1
1
1
1
0
1
1
0
1
1
0
1
1
0
0
1
1
Timing:
For B
i
0
M cycles D 5
T states D 21 (4, 5, 3, 4, 5)
For B
e
0
M cycles D 4
T states D 16 (4, 5, 3, 4)
Addressing Mode:
Implied/Source D Register In-
direct
Destination D Register Indirect
(Note that at the end of each data transfer cycle, interrupts
may be recognized and two refresh cycles will be per-
formed.)
53
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NSC858 | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858D | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858E | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858N | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858V | NSC858 Universal Asynchronous Receiver/Transmitter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NSC800V-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microprocessor |
| NSC810AD | 制造商:National Semiconductor Corporation 功能描述:22 I/O, PIA-GENERAL PURPOSE, 40 Pin Ceramic DIP |
| NSC810AD/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| NSC810AD-1/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RAM I/O Timer |
| NSC810AD-1/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RAM I/O Timer |
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