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參數(shù)資料
| 型號： | NSC800V |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NSC800TM High-Performance Low-Power CMOS Microprocessor |
| 中文描述： | NSC800TM高性能低功耗CMOS微處理器 |
| 文件頁數(shù)： | 15/76頁 |
| 文件大?。?/td> | 785K |
| 代理商： | NSC800V |
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9.0 Timing and Control
9.1 INTERNAL CLOCK GENERATOR
An inverter oscillator contained on the NSC800 chip pro-
vides all necessary timing signals. The chip operation fre-
quency is equal to one half of the frequency of this oscilla-
tor.
The oscillator frequency can be controlled by one of the
following methods:
1. Leaving the X
OUT
pin unterminated and driving the X
IN
pin with an externally generated clock as shown inFigure
6. When driving X
IN
with a square wave, the minimum
duty cycle is 30% high.
TL/C/5171–13
FIGURE 6. Use of External Clock
2. Connecting a crystal with the proper biasing network be-
tween X
IN
and X
OUT
as shown inFigure 7. Recommend-
ed crystal is a parallel resonance AT cut crystal.
Note 1:
If the crystal frequency is between 1 MHz and 2 MHz a series
resistor, R
S
, (470
X
to 1500
X
) should be connected between
X
OUT
and R, XTAL and C
Z
. Additionally, the capacitance of C1
and C2 should be increased by 2 to 3 times the recommended
value. For crystal frequencies less than 1 MHz higher values of
C1 and C2 may be required. Crystal parameters will also affect
the capacitive loading requirements.
2 MHz
k
f(XTAL)
2
R
e
1 M
X
C1
e
20 pF
C2
e
34 pF
(Recommended)
TL/C/5171–14
FIGURE 7. Use Of Crystal
The CPU has a minimum clock frequency input (
@
X
IN
) of
300 kHz, which results in 150 kHz system clock speed. All
registers internal to the chip are static, however there is
dynamic logic which limits the minimum clock speed. The
input clock can be stopped without fear of losing any data or
damaging the part. You stop it in the phase of the clock that
has X
IN
low and CLK OUT high. When restarting the CPU,
precautions must be taken so that the input clock meets
these minimum specification. Once started, the CPU will
continue operation from the same location at which it was
stopped. During DC operation of the CPU, typical current
drain will be 2 mA. This current drain can be reduced by
placing the CPU in a wait state during an opcode fetch cycle
then stopping the clock. For clock stop circuit, seeFigure 8.
TL/C/5171–36
FIGURE 8. Clock Stop Circuit
15
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PDF描述 |
|---|---|
| NSC858 | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858D | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858E | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858N | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858V | NSC858 Universal Asynchronous Receiver/Transmitter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NSC800V-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microprocessor |
| NSC810AD | 制造商:National Semiconductor Corporation 功能描述:22 I/O, PIA-GENERAL PURPOSE, 40 Pin Ceramic DIP |
| NSC810AD/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| NSC810AD-1/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RAM I/O Timer |
| NSC810AD-1/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RAM I/O Timer |
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