參數(shù)資料
型號: NSC800V
廠商: National Semiconductor Corporation
英文描述: NSC800TM High-Performance Low-Power CMOS Microprocessor
中文描述: NSC800TM高性能低功耗CMOS微處理器
文件頁數(shù): 33/76頁
文件大?。?/td> 785K
代理商: NSC800V
12.4 8-Bit Loads
(Continued)
LD
m
2
, A
Load memory from the Accumulator.
m
2
w
A
7
6
5
4
3
No flags affected
0
2
1
0
0
0
0
0
0
1
0
LD (BC), A
0
0
0
1
0
0
1
0
LD (DE), A
Timing:
M cycles D 2
T states D 7 (4, 3)
Addressing Mode:
Source D Register (Implied)
Destination D Register Indirect
0
7
6
5
4
3
2
1
0
0
1
1
0
0
1
0
LD (nn), A
n (low-order byte)
n (high-order byte)
Timing:
M cycles D 4
T states D 3 (4, 3, 3, 3)
Addressing Mode:
Source D Register (Implied)
Destination D Direct
LD
m
1
, n
Load memory with immediate data.
m
1
w
n
7
6
5
4
3
No flags affected
0
2
1
0
0
1
1
0
1
1
0
LD(HL), n
n
Timing:
M cyclesD3
T statesD10 (4, 3, 3)
Addressing Mode:
SourceDImmediate
DestinationDRegister Indirect
7
6
5
4
3
2
1
0
LD (IX
a
d), n(for N
X
e
0)
1
1
N
X
1
1
1
0
1
LD (IY
a
d), n(for N
X
e
1)
0
0
1
1
0
1
1
0
d
n
Timing:
M cyclesD5
T statesD19 (4, 4, 3, 5, 3)
Addressing Mode:
SourceDImmediate
DestinationDIndexed
MEMORY TO REGISTER
LD
r, m
1
Load register r from memory location m
1
.
r
w
m
1
7
6
5
4
3
2
No flags affected
0
1
0
1
r
1
1
0
LD R, (HL)
Timing:
M cyclesD2
T statesD7 (4, 3)
Addressing Mode:
SourceDRegister Indirect
DestinationDRegister
0
LD r, (IX
a
d) (for N
X
e
0)
1
LD r, (IY
a
d) (for N
X
e
1)
7
6
5
4
3
2
1
1
1
N
X
1
1
1
0
0
1
r
1
1
0
d
Timing:
M cyclesD5
T statesD19 (4, 4, 3, 5, 3)
Addressing Mode:
SourceDIndexed
DestinationDRegister
LD
A, m
2
Load the Accumulator from memory location m
2
.
A
w
m
2
7
6
5
4
3
2
1
No flags affected
0
LD A, (BC)
0
0
0
0
0
1
0
1
0
0
0
1
1
0
1
0
LD A, (DE)
Timing:
M cyclesD2
T statesD7 (4, 3)
Addressing Mode:
SourceDRegister Indirect
DestinationDRegister (Implied)
0
7
6
5
4
3
2
1
0
0
1
1
1
0
1
0
LD A, (nn)
n (low-order byte)
n (high-order byte)
Timing:
M cyclesD4
T statesD13 (4, 3, 3, 3)
Addressing Mode:
SourceDImmediate Extended
DestinationDRegister (Implied)
33
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相關代理商/技術參數(shù)
參數(shù)描述
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