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參數(shù)資料
| 型號(hào)： | NSC800V |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NSC800TM High-Performance Low-Power CMOS Microprocessor |
| 中文描述： | NSC800TM高性能低功耗CMOS微處理器 |
| 文件頁(yè)數(shù)： | 51/76頁(yè) |
| 文件大小： | 785K |
| 代理商： | NSC800V |
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12.11 Memory Block Moves and Searches
(Continued)
7
6
5
4
3
2
1
0
1
1
1
0
1
1
0
1
1
0
1
0
1
0
0
1
Timing:
M cycles D 4
T states D 16 (4, 4, 3, 5)
Addressing Mode:
Register Indirect
REPEAT OPERATIONS
LDIR
Move data from memory location (HL) to memory location
(DE), increment memory pointers, decrement byte counter
BC, and repeat until BC
e
0.
(DE)
w
(HL)
S: N/A
DE
w
DE
a
1
Z: N/A
HL
w
HL
a
1
H: Reset
BC
w
BC
b
1
P/V: Reset
Repeat until
N: Reset
BC
e
0
C: N/A
7
6
5
4
3
2
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
0
0
0
Timing:
For BC
i
0 M cycles D 5
T states D 21 (4, 4, 3, 5, 5)
For BC
e
0 M cycles D 4
T states D 16 (4, 4, 3, 5)
Addressing Mode:
Register Indirect
(Note that each repeat is accomplished by a decrement of
the BC, so that refresh, etc. continues for each cycle.)
LDDR
Move data from memory location (HL) to memory location
(DE), decrement memory pointers and byte counter BC, and
repeat until BC
e
0.
(DE)
w
(HL)
S: N/A
DE
w
DE
b
1
Z: N/A
HL
w
HL
b
1
H: Reset
BC
w
BC
b
1
P/V: Reset
Repeat until
N: Reset
BC
e
0
C: N/A
7
6
5
4
3
2
1
0
1
1
1
0
1
1
0
1
1
0
1
1
1
0
0
0
Timing:
For BC
i
0 M cycles D 5
T states D 21 (4, 4, 3, 5, 5)
For BC
e
0 M cycles D 4
T states D 16 (4, 4, 3, 5)
Addressing Mode:
Register Indirect
(Note that each repeat is accomplished by a decrement of
the BC, so that refresh, etc. continues for each cycle.)
CPIR
Compare data in memory location (HL) to the Accumulator,
increment the memory, decrement the byte counter BC, and
repeat until BC
e
0 or (HL) equals A.
A
b
(HL)
S: Set if sign of subtraction per-
formed for comparison is nega-
HL
w
HL
a
1
tive
BC
w
BC
b
1
Z: Set if A
e
(HL), otherwise reset
Repeat until BC
e
0
H: Set according to borrow from
or A
e
(HL)
bit 4
P/V: Set if BC
b
1
i
0, otherwise
reset
N: Set
C: N/A
1
0
7
6
5
4
3
2
1
1
1
0
1
1
0
1
1
0
1
1
0
0
0
1
Timing:
For BC
i
0
M cycles D 5
T states D 21 (4, 4, 3, 5, 5)
For BC
e
0
M cycles D 4
T states D 16 (4, 4, 3, 5)
Addressing Mode:
Register Indirect
(Note that each repeat is accomplished by a decrement of
the PC, so that refresh, etc. continues for each cycle.)
CPDR
Compare data in memory location (HL) to the contents of
the Accumulator, decrement the memory pointer and byte
counter BC, and repeat until BC
e
0, or until (HL) equals
the Accumulator.
A
b
(HL)
S: Set if sign of subtraction per-
formed for comparison is nega-
HL
w
HL
b
1
tive
BC
w
BC
b
1
Z: Set according to equality of A
Repeat until BC
e
0
and (HL), set if true
or A
e
(HL)
H: Set according to borrow from
bit 4
P/V: Set if BC
b
1
i
0, otherwise
reset
N: Set
C: N/A
1
0
7
6
5
4
3
2
1
1
1
0
1
1
0
1
1
0
1
1
1
0
0
1
Timing:
For BC
i
0
M cycles D 5
T states D 21 (4, 4, 3, 5, 5)
For BC
e
0
M cycles D 4
T states D 16 (4, 4, 3, 5)
Addressing Mode:
Register Indirect
(Note that each repeat is accomplished by a decrement of
the BC, so that refresh, etc. continues for each cycle.)
51
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NSC858 | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858D | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858E | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858N | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858V | NSC858 Universal Asynchronous Receiver/Transmitter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NSC800V-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microprocessor |
| NSC810AD | 制造商:National Semiconductor Corporation 功能描述:22 I/O, PIA-GENERAL PURPOSE, 40 Pin Ceramic DIP |
| NSC810AD/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| NSC810AD-1/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RAM I/O Timer |
| NSC810AD-1/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RAM I/O Timer |
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