參數(shù)資料
型號(hào)： NS16C2752
廠商： National Semiconductor Corporation
英文描述： Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate
中文描述： 雙UART與16-byte/64-byte FIFO和高達(dá)5 Mbit / s的數(shù)據(jù)速率
文件頁(yè)數(shù)： 16/43頁(yè)
文件大?。?/td> 881K
代理商： NS16C2752
6.0 Register Set
(Continued)
6.6 LINE CONTROL REGISTER (LCR)
The system programmer specifies the format of the asyn-
chronous data communications exchange and sets the Divi-
sor Latch Access bit via the Line Control Register (LCR).
This is a read and write register.
TABLE 10. LCR (0x3)
Bit
7
Bit Name
Default
Divisor Latch
Ena
R/W
Def
R/W
0
Description
Divisor Latch Access Bit (DLAB)
This bit must be set (logic 1) to access the Divisor Latches of the Baud Generator
and the Alternate Function Register during a read or write operation. It must be
cleared (logic 0) to access any other register.
1 = Enable access to the Divisor Latches of the Baud Generator and the AFR.
0 = Enable access to other registers (default).
Set Tx Break Enable
This bit is the Break Control bit. It causes a break condition to be transmitted to the
receiving UART. The Break Control bit acts only on SOUT and has no effect on the
transmitter logic.
1 = Serial output (SOUT) is forced to the Spacing State (break state, logic 0).
0 = The break transmission is disabled (default).
Note: This feature enables the CPU to alert a terminal in a computer communication
system. If the following sequence is followed, no erroneous or extraneous character
will be transmitted because of the break.
1. Load an all 0s, pad character, in response to THRE.
2. Set break after the next THRE.
3. Wait for the transmitter to be idle, (Transmitter Empty TEMT = 1), and clear break
when normal transmission has to be restored.
During the break, the transmitter can be used as a character timer to establish the
break duration.
During the break state, any word left in THR will be shifted out of the register but
blocked by SOUT as forced to break state. This word will be lost.
Tx and Rx Forced Parity Select
When parity is enabled, this bit selects the forced parity format.
6
Tx Break
Ena
R/W
0
5
Forced
Parity Sel
R/W
0
LCR[5]
1
1
0
0
X
Tx and Rx Even/Odd Parity Select
This bit is only effective when LCR[3]=1. This bit selects even or odd parity format.
1 = Odd parity is transmitted or checked.
0 = Even parity is transmitted or checked (default).
Tx and Rx Parity Enable
This bit enables parity generation.
1 = A parity is generated during the data transmission. The receiver checks for parity
error of the data received.
0 = No parity (default).
LCR[4]
1
0
1
0
X
LCR[3]
1
1
1
1
0
Parity Select
Force parity to space = 0
Force parity to mark = 1
Even parity
Odd parity
No parity
4
Even/Odd
Parity Sel
R/W
0
3
Tx/Rx Parity
Ena
R/W
0
N
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相關(guān)PDF資料
PDF描述
NS16C2752TVA Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate
NS32203D DIRECT MEMORY ACCESS CONTROLLER
NS32203N DIRECT MEMORY ACCESS CONTROLLER
NS32382-10 MEMORY MANAGEMENT UNITS
NS32382-15 MEMORY MANAGEMENT UNITS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NS16C2752TVA 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate
NS16C2752TVA/NOPB 功能描述:UART 接口集成電路 RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
NS16C2752TVAX/NOPB 功能描述:UART 接口集成電路 Dual UART w/ 64-byte FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
NS16C2752TVS 制造商:Texas Instruments 功能描述:UART 2-CH 64Byte FIFO 3.3V/5V 48-Pin TQFP
NS16C2752TVS/NOPB 功能描述:UART 接口集成電路 RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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