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參數(shù)資料
| 型號： | NS16C2752 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate |
| 中文描述： | 雙UART與16-byte/64-byte FIFO和高達(dá)5 Mbit / s的數(shù)據(jù)速率 |
| 文件頁數(shù)： | 15/43頁 |
| 文件大?。?/td> | 881K |
| 代理商： | NS16C2752 |
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6.0 Register Set
(Continued)
TABLE 9. FCR (0x2)
(Continued)
Bit
5:4
Bit
Name
Tx FIFO
Trig
Level Sel
R/W
Def
W
00
Description
Transmit FIFO Trigger Level Selection
The transmit FIFO trigger threshold selection is only available in NS16C2752. When
enabled, a transmit interrupt is generated and TXRDY is asserted when the number of empty
spaces in the FIFO exceeds the threshold level.
For NS16C2752 with 64-byte FIFO:
FCR[5]
FCR[4]
Tx FIFO Trigger Level
1
1
= 56
1
0
= 32
0
1
= 16
0
0
= 8 (Default)
Refer to
Section 7.4 TRANSMIT OPERATION
and
Section 7.9 DMA OPERATION
for
transmit FIFO descriptions.
These two bits are reserved in NS16C2552 and have no impact when they are written to.
DMA Mode Select
This bit controls the RXRDY and TXRDY initiated DMA transfer mode.
1 = DMA Mode 1. Allows block transfers. Requires FCR 0x2.0=1 (FIFO mode).
0 = DMA Mode 0 (default). Single transfers.
Transmit FIFO Reset
This bit is only active when FCR bit 0 = 1.
1 = Reset XMIT FIFO pointers and all bytes in the XMIT FIFO (the Tx shift register is not
cleared and is cleared by MR reset). This bit has the self-clearing capability.
0 = No impact (default).
3
DMA
Mode
Select
W
0
2
Tx FIFO
Reset
W
0
Note:
Reset pointer will cause the characters in Tx FIFO to be lost.
Receive FIFO Reset
This bit is only active when FCR bit 0 = 1.
1 = Reset RCVR FIFO pointers and all bytes in the RCVR FIFO (the Rx shift register is not
cleared and is cleared by MR reset). This bit has the self-clearing capability.
0 = No impact (default).
1
Rx FIFO
Reset
W
0
Note:
Reset pointer will cause the characters in Rx FIFO to be lost.
Transmit and Receive FIFO Enable
1 = Enable transmit and receive FIFO. This bit must be set before other FCR bits are
written. Otherwise, the FCR bits can not be programmed.
0 = Disable transmit and receive FIFO (default).
0
Tx and
Rx FIFO
Enable
W
0
N
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NS16C2752TVA | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate |
| NS16C2752TVA/NOPB | 功能描述:UART 接口集成電路 RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| NS16C2752TVAX/NOPB | 功能描述:UART 接口集成電路 Dual UART w/ 64-byte FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| NS16C2752TVS | 制造商:Texas Instruments 功能描述:UART 2-CH 64Byte FIFO 3.3V/5V 48-Pin TQFP |
| NS16C2752TVS/NOPB | 功能描述:UART 接口集成電路 RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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