參數(shù)資料
型號(hào)： NS16C2752
廠商： National Semiconductor Corporation
英文描述： Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate
中文描述： 雙UART與16-byte/64-byte FIFO和高達(dá)5 Mbit / s的數(shù)據(jù)速率
文件頁(yè)數(shù)： 14/43頁(yè)
文件大?。?/td> 881K
代理商： NS16C2752
6.0 Register Set
(Continued)
TABLE 8. Interrupt Sources and Clearing
(Continued)
Interrupt
Generation
Rx Trigger
Interrupt Sources
Interrupt Clearing
Rx FIFO reached trigger level.
Read FIFO data until FIFO pointer falls below the
trigger level.
Read RBR.
RXRDY
Timer
TXRDY
MSR
Xoff or
Special
character
CTS
Time-out in 4-word time plus 12-bit delay time.
THR empty.
Any state change in MSR[3:0].
Detection of Xoff or Special character.
Read from IIR register or a write to THR.
Read from MSR register.
Read from IIR register or reception of Xon character
(or reception of next character if interrupt is caused by
Special character).
Read from IIR or MSR.
Input pin toggles from logic 0 to 1 during CTS
auto flow control mode.
Output pin toggles from logic 0 to 1 during RTS
auto flow control mode.
RTS
Read from IIR or MSR.
6.5 FIFO CONTROL REGISTER (FCR)
This is a write only register at the same location as the IIR
(the IIR is a read only register). This register is used to
enable the FIFOs, clear the FIFOs, set the FIFO trigger level,
and select the DMA mode.
Mode 0:
Mode 0 allows for single transfer in each DMA
cycle. When in the 16450 Mode (FCR[0] = 0) or in the FIFO
Mode (FCR[0] = 1, FCR[3] = 0) and there is at least one
character in the RCVR FIFO or RCVR Buffer Register, the
RXRDY pin will go active low. After going active, the RXRDY
pin will be inactive when there is no character in the FIFO or
Buffer Register.
On The Tx side, TXRDY is active low when XMIT FIFO or
XMIT Holding Register is empty. TXRDY returns to high
when XMIT FIFO or XMIT holding register is not empty.
Mode 1:
Mode 1 allows for multiple transfer or multi-
character burst transfer. In the FIFO Mode (FCR[0] = 1,
FCR[3] = 1) when the number of characters in the RCVR
FIFO equals the trigger threshold level or timeout occurs, the
RXRDY goes active low to initiate DMAtransfer request. The
RXRDY returns high when RCVR FIFO becomes empty.
In the FIFO Mode (FCR[0] = 1, FCR[3] = 1) when there is (1)
no character in the XMIT FIFO for NS16C2552, or (2) empty
spaces exceed the threshold level for NS16C2752; the
TXRDY pin will go active low. This pin will become inactive
when the XMIT FIFO is completely full.
TABLE 9. FCR (0x2)
Bit
7:6
Bit
Name
Rx FIFO
Trig
Select
R/W
Def
W
00
Description
Rx FIFO Trigger Select
FCR[6] and FCR[7] are used to designate the interrupt trigger level. When the number of
characters in the RCVR FIFO equals the designated interrupt trigger level, a Received Data
Available Interrupt is activated. This interrupt must be enabled by IER[0]=1.
For NS16C2552 with 16-byte FIFO:
FCR[7]
FCR[6]
Rx FIFO Trigger Level
1
1
= 14
1
0
= 8
0
1
= 4
0
0
= 1 (Default)
For NS16C2752 with 64-byte FIFO:
FCR[7]
FCR[6]
Rx FIFO Trigger Level
1
1
= 60
1
0
= 56
0
1
= 16
0
0
= 8 (Default)
Refer to
Section 7.5 SOFTWARE XON/XOFF FLOW CONTROL
and
Section 7.9 DMA
OPERATION
for software flow control using FIFO trigger level.
N
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NS16C2752TVA 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate
NS16C2752TVA/NOPB 功能描述:UART 接口集成電路 RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
NS16C2752TVAX/NOPB 功能描述:UART 接口集成電路 Dual UART w/ 64-byte FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
NS16C2752TVS 制造商:Texas Instruments 功能描述:UART 2-CH 64Byte FIFO 3.3V/5V 48-Pin TQFP
NS16C2752TVS/NOPB 功能描述:UART 接口集成電路 RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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