參數(shù)資料
型號(hào)： NS16C2752
廠商： National Semiconductor Corporation
英文描述： Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate
中文描述： 雙UART與16-byte/64-byte FIFO和高達(dá)5 Mbit / s的數(shù)據(jù)速率
文件頁(yè)數(shù)： 12/43頁(yè)
文件大小： 881K
代理商： NS16C2752
6.0 Register Set
(Continued)
TABLE 3. RBR (0x0)
Bit
7:0
Bit Name
RBR Data
R/W Def
R
0xXX
Description
Receive Buffer Register
Rx FIFO data.
Note:
This register value does not change upon MR reset.
6.2 TRANSMIT HOLDING REGISTER (THR)
This register holds the byte-wide transmit data (THR). This is
a write-only register.
TABLE 4. THR (0x0)
Bit
7:0
Bit Name
THR Data
R/W Def
W
0xXX
Description
Transmit Holding Register
Tx FIFO data.
Note:
This register value does not change upon MR reset.
6.3 INTERRUPT ENABLE REGISTER (IER)
This register enables eight types of interrupts for the corre-
sponding serial channel. Each interrupt source can individu-
ally activate the interrupt (INTR) output signal. Setting the
bits of the IER to a logic 1 unmasks the selected interrupt(s).
Similarly, the interrupt can be masked off by resetting bits 0
through 7 of the Interrupt Enable Register (IER). If not de-
sired to be used, masking an interrupt source prevents it
from going active in the IIR and activating the INTR output
signal. While interrupt sources are masked off, all system
functions including the Line Status and MODEM Status still
operate in their normal manner.
Table 5
shows the contents
of the IER.
TABLE 5. IER (0x1)
Bit
7
Bit Name
CTS Int Ena
R/W
Def
R/W
0
Description
CTS Input Interrupt Enable
1 = Enable the CTS to generate interrupt at low to high transition. Requires EFR 0x2.4 = 1.
0 = Disable the CTS interrupt (default).
RTS Output Interrupt Enable
1 = Enable the RTS to generate interrupt at low to high transition. Requires EFR 0x2.4 = 1.
0 = Disable the RTS interrupt (default).
Xoff Input Interrupt Enable
1 = Enable the software flow control character Xoff to generate interrupt. Requires EFR
0x2.4 = 1.
0 = Disable the Xoff interrupt (default).
Sleep Mode Enable
1 = Enable the Sleep Mode for the respective channel. Requires EFR 0x2.4 = 1.
0 = Disable Sleep Mode (default).
Modem Status Interrupt Enable
1 = Enable the Modem Status Register interrupt.
0 = Disable the Modem Status Register interrupt (default).
Receive Line Status Interrupt Enable
An interrupt can be generated when any of the LSR bits 0x5.4:1=1. LSR 0x5.1 generates
an interrupt as soon as an overflow frame is received. LSR 0x5.4:2 generate an interrupt
when there is read error from FIFO.
1 = Enable the receive line status interrupt.
0 = Disable the receive line status interrupt (default).
Tx Holding Reg Empty Interrupt Enable
1 = Enable the interrupt when Tx Holding Register is empty.
0 = Disable the Tx Holding Register from generating interrupt (default).
6
RTS Int Ena
R/W
0
5
Xoff Int Ena
R/W
0
4
Sleep Mode
Ena
R/W
0
3
Mdm Stat Int
Ena
R/W
0
2
Rx Line Stat
Int Ena
R/W
0
1
Tx_Empty Int
Ena
R/W
0
N
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參數(shù)描述
NS16C2752TVA 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate
NS16C2752TVA/NOPB 功能描述:UART 接口集成電路 RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
NS16C2752TVAX/NOPB 功能描述:UART 接口集成電路 Dual UART w/ 64-byte FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
NS16C2752TVS 制造商:Texas Instruments 功能描述:UART 2-CH 64Byte FIFO 3.3V/5V 48-Pin TQFP
NS16C2752TVS/NOPB 功能描述:UART 接口集成電路 RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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