參數(shù)資料
型號: NDS356
廠商: Fairchild Semiconductor Corporation
英文描述: P-Channel Logic Level Enhancement Mode Field Effect Transistor
中文描述: P溝道增強(qiáng)模式的邏輯電平場效應(yīng)晶體管
文件頁數(shù): 6/6頁
文件大小: 78K
代理商: NDS356
NDS356AP Rev.C
1
Figure 14. Maximum Safe Operating Area
.
Typical Electrical Characteristics
(continued)
Figure 17. Transient Thermal Response Curve.
Note : Characterization performed using the conditions described in note 1b. Transient thermal response will
change depending on the circuit board design.
-5
-4
-3
-2
-1
0
0
1
2
3
4
5
I , DRAIN CURRENT (A)
g
TJ
25°C
F
V = - 5V
DS
125°C
0.1
0.2
0.5
1
2
5
10
20
30
0.01
0.05
0.1
0.5
1
2
5
10
20
- V , DRAIN-SOURCE VOLTAGE (V)
-
D
RDS(ON) LIMIT
A
DC
1s
100ms
10ms
1ms
V = -4.5V
SINGLE PULSE
R = See Note 1b
T = 25°C
100us
0
0.1
0.2
0.3
0.4
0.8
0.9
1
1.1
1.2
1.3
1.4
2oz COPPER MOUNTING PAD AREA (in )
-
2
1b
1a
D
4.5"x5" FR-4 Board
T = 25 C
Still Air
V = -4.5V
0
0.1
0.2
0.3
0.4
0
0.2
0.4
0.6
0.8
1
2oz COPPER MOUNTING PAD AREA (in )
S
2
1b
1a
4.5"x5" FR-4 Board
T = 25 C
Still Air
A
Figue 15. SuperSOT
TM _
3 Maximum
Steady-State Power Dissipation versus
Copper Mounting Pad Area.
Figure 13. Transconductance Variation with Drain
Current and Temperature
.
Figure 16. Maximum Steady-State Drain
Current versus Copper Mounting Pad Area.
0.0001
0.001
0.01
0.1
t , TIME (sec)
1
10
100
300
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
T
Duty Cycle, D = t /t
2
R (t) = r(t) * R
R = See Note 1b
T - T = P * R JA
P(pk)
t
1
t
2
r
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
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