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參數(shù)資料
| 型號(hào)： | NDS356P |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 小信號(hào)晶體管 |
| 英文描述： | P-Channel Logic Level Enhancement Mode Field Effect Transistor（-1.1A，-20V，0.3Ω）(P溝道邏輯增強(qiáng)型MOS場(chǎng)效應(yīng)管（漏電流-1.1A, 漏源電壓-20V，導(dǎo)通電阻0.3Ω）) |
| 中文描述： | 1100 mA, 20 V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET |
| 封裝： | SUPERSOT-3 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 78K |
| 代理商： | NDS356P |
March 1996
NDS356P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
_______________________________________________________________________________
Absolute Maximum Ratings
Symbol
Parameter
T
A
= 25°C unless otherwise noted
NDS356P
Units
V
DSS
Drain-Source Voltage
-20
V
V
GSS
I
D
Gate-Source Voltage - Continuous
± 12
V
Maximum Drain Current
- Continuous
(Note 1a)
±1.1
A
- Pulsed
±10
P
D
Maximum Power Dissipation
(Note 1a)
0.5
W
(Note 1b)
0.46
T
J
,T
STG
Operating and Storage Temperature Range
-55 to 150
°C
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
250
°C/W
R
θ
JC
Thermal Resistance, Junction-to-Case
(Note 1)
75
°C/W
NDS356P Rev. E1
These P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications such as
notebook computer power management, portable
electronics, and other battery powered circuits where
fast high-side switching, and low in-line power loss are
needed in a very small outline surface mount package.
-1.1 A, -20V. R
DS(ON)
= 0.3
@ V
GS
= -4.5V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
D
S
G
1997 Fairchild Semiconductor Corporation
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