參數(shù)資料
型號： NCN6001DTBEVB
廠商： ON Semiconductor
文件頁數(shù)： 14/36頁
文件大小： 0K
描述： EVAL BOARD FOR NCN6001DTB
設(shè)計資源： NCN6001DTBEVB Gerber Files
NCN6001 Demo Brd Schematic
NCN6001DBEVB BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，智能卡
嵌入式： 是，MCU，8 位
已用 IC / 零件： NCN6001
主要屬性： 與 ISO 7816-3，EMV，GIE-CB 兼容
次要屬性： 符合 GSM 規(guī)定
已供物品： 板
其它名稱： NCN6001DTBEVBOS
NCN6001
http://onsemi.com
21
When the eight bits transfer is completed, the content of
the internal shift register is latched on the positive going
edge of the CS signal and the NCN6001 related functions are
updated accordingly.
Figure 14. Basic Multi Command SPI Bytes
Select Chip from SYNCHRONOUS Bank
Chip Ny
Chip Nx
tdclk
Special Mode: MISO
is synchronized with
the SPI_CLK Positive
going slope
Normal Mode: MISO is synchronized with
the SPI_CLK Negative going slope
MISO Line = High Impedance
B0
B1
B2
B3
B4
B5
B6
B7
B0
B1
B2
B3
B4
B5
B6
B7
SPI_CLK
CS
MOSI
SET_RST
SET_CLK
SET_VCC
ADDRESS
DECODE
CHIP
ADDRESS
COMMAND
AND CONTROL
MSB
LSB
MISO
Special Mode
MISO
Normal Mode
MPU Enables
Clock
Since the four chips present in the Asynchronous Bank
have an individual physical address, the system can control
several of these chips by sending the data content within the
same CS frame as depicted in Figure 14. The bits are
decoded on the fly and the related sub blocks are updated
accordingly. According to the SPI general specification, no
code or activity will be transferred to any chip when the CS
is High.
When two SPI bytes are sequentially transferred on the
MOSI line, the CLK_SPI sequence must be separated by at
least one half positive period of this clock (see tdclk
parameter).
The oscillograms shown in Figure 15 and Figure 16
illustrate the SPI communication protocol (source:
NCN6001 demo board).
Figure 15. Programming Sequence, Chip Address = $03
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