參數(shù)資料
型號： NCN6001DTBEVB
廠商： ON Semiconductor
文件頁數(shù)： 11/36頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR NCN6001DTB
設計資源： NCN6001DTBEVB Gerber Files
NCN6001 Demo Brd Schematic
NCN6001DBEVB BOM
標準包裝： 1
主要目的： 接口，智能卡
嵌入式： 是，MCU，8 位
已用 IC / 零件： NCN6001
主要屬性： 與 ISO 7816-3，EMV，GIE-CB 兼容
次要屬性： 符合 GSM 規(guī)定
已供物品： 板
其它名稱： NCN6001DTBEVBOS
NCN6001
http://onsemi.com
19
INTERRUPT
When the system is powered up, the INT pin is set to High
upon POR signal. The interrupt pin 2 is forced LOW when
either a card is inserted/extracted, or when a fault is
developed across the CRD_VCC output voltage. This signal
is neither combined with the CS signal, nor with the chip
address. Consequently, an interrupt is placed on the
mC input
as soon as one of the condition is met.
The INT signal is clear to High upon one of the condition
given in Table 7.
Table 7. INTERRUPT RESET LOGIC
Interrupt Source
CS
CRD_VCC
Chip Address
Card Insertion
L
> 0
Selected Chip MOSI[b7 : B5] = 0xx or MOSI[b7 : B5] = 101
Card Insertion
L
= 0
Selected Chip MOSI[b7 :B5] = 0xx or MOSI[b7 : B5] = 101
Over Load
L
= 0
Selected Chip MOSI[b7 : B5] = 0xx or MOSI[b7 : B5] = 101
When several interfaces share the same digital
mC bus, it is up to the software to pool the chips, using the MISO register to
identify the source of the interrupt.
Figure 11. Basic Interrupt Function
CS
INT
CRD_DET
MOSI_b0
MOSI_b1
CRD_VCC > 0 V
CRD_VCC = 0 V
OVER LOAD
CRD_VCC
T0
T2
T10
T3
T4
T9
T6
T7
T8
T5
T1
T11
1
2
3
Table 8. INTERRUPT RESET LOGIC OPERATION
T0
A card has been inserted into the reader and detected by the CRD_DET signal. The NCN6001 pulls down the interrupt line.
T1
The mC sets the CS signal to Low, the chip is now active, assuming the right address has been placed by the MOSI register.
T2
The mC acknowledges the interrupt and resets the INT to High by the MOSI [B1 : B0 ] logic state: CRD_VCC is programmed
higher than zero volt.
T3
The card has been extracted from the reader, CRD_DET goes Low and an interrupt is set (INT = L). On the other hand, the
PWR_DOWN sequence is activated by the NCN6001.
T4
The interrupt pin is clear by the zero volt programmed to the interface.
T5
Same as T0
T6
The mC start the DC/DC converter, the interrupt is cleared (same as T2)
T7
An overload has been detected by the chip : the CRD_VCC voltage is zero, the INT goes Low.
T8
The card is extracted from the reader, CRD_DET goes Low and an interrupt is set (INT = L).
T9
The card is reinserted before the interrupt is acknowledged by the mC: the INT pin stays Low.
T10
The mC acknowledges the interrupt and reset the INT to High by the MOSI [B1 : B0 ] logic state: CRD_VCC is programmed
higher than zero volt.
T11
The Chip Select signal goes High, all the related NCN6001 interface(s) are deactivated and no further programming or
transaction can take place.
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