參數(shù)資料
型號: MX98725
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE CHIP FAST ETHERNET NIC CONTROLLER
中文描述: 單晶片快速以太網(wǎng)卡控制器
文件頁數(shù): 9/33頁
文件大小: 177K
代理商: MX98725
9
P/N:PM0488
REV. 1.7, SEP. 15, 1998
MX98725
5.1.8 PCI CAPABILITY POINTER REGISTER ( PFCP ) ( Offset 37h-34h )
5.1.9 INTERRUPT REGISTER ( PFIT ) ( Offset 3Fh-3Ch )
5.1.10 PCI DRIVER AREA REGISTER ( PFDA ) ( 43h-40h )
bit 7- 0 : Capability pointer (Cap_Ptr) is set to 44h if PMEB is connected to PCI bus, otherwise 00.
bit 31- 8 : reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Capability Pointer (Set to 44h)
bit 7 - 0 : Interrupt Line, system BIOS will writes the routing information into this field, driver can use this information
to determine priority and interrupt vector.
bit 15 - 8 : Interrupt Pin, fixed to 01h which use INTA#.
bit 31 - 24 : Max_Lat which is a maximum period for a access to PCI bus.
bit 23 - 16 : Min_Gnt which is the maximum period that MX98725 needs to finish a brust PCI cycle.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Min-Gnt
Interrupt Pin
Interrupt Line
Max_Lat
0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0
bit 31 : Sleep Mode, set to sleep mode which allows access to PCI configuration space, a hardwarreset or reset to
this bit can exit from sleep mode. Magic packet can be received under sleep mode if CSR16<21> ( Magic
Packet Enable ) is set.
bit 30 : not used
bit 29 : board type
bit 15 - 8 : driver is free to read and write this field for any purpose.
bit 7 - 0 : not used.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Sleep Mode
Board Type
Driver Special Use
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