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參數(shù)資料
| 型號(hào)： | MX98725 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE CHIP FAST ETHERNET NIC CONTROLLER |
| 中文描述： | 單晶片快速以太網(wǎng)卡控制器 |
| 文件頁數(shù)： | 12/33頁 |
| 文件大小： | 177K |
| 代理商： | MX98725 |
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12
P/N:PM0488
REV. 1.7, SEP. 15, 1998
MX98725
5.2.1 BUS MODE REGISTER ( CSR0 )
Field
0
Name
SWR
Description
Software Reset, when set, MX98725 resets all internal hardware with the exception of the
configuration area and port selection.
Internal bus arbitration scheme between receive and transmit processes.
The receive channel usually has higher priority over transmit channel when receive FIFO
is partially full to a threshold. This threshold can be selected by programming this bit. Set
for lower threshold, reset for normal threshold.
Descriptor Skip Length, specifies the number of longwords to skip between two
descriptors.
Big/Little Endian, set for big endian byte ordering mode, reset for little endian byte ordering
mode, this option only applies to data buffers
Programmable Burst Length, specifies the maximum number of longwords to be trans
ferred in one DMA transaction. default is 0 which means unlimited burst length, possible
values can be 1,2,4,8,16,32 and unlimited .
Cache Alignment, programmable address boundaries of data burst stop, MX98725 can
handle non-cache- aligned fragement as well as cache-aligned fragment efficiently.18:17
TAP Transmit Auto-Polling time interval, defines the time interval for MX98725 to performs
transmit poll command automatically at transmit suspended state.
PCI Memory Read Multiple command enable, indicates bus master may intend to fetch
more than one cache lines disconnecting.
PCI Memory Read Line command enable, indicating bus master intends to fetch a
complete cache line.
PCI Memory Write and Invalidate command enable, guarantees a minimum transfer of
one complete cache line.
1
BAR
6:2
DSL
7
BLE
13:8
PBL
15:14
CAL
21
RME
23
RLE
24
WIE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIE-Write and Invalidate Enable
PLE-Read Line Enable
RME-Read Multiple Enable
TAP- Transmit Automatice Polling
ZERO-Must be zero
CAL-Cache Alignment
SWR-Software Read
BLE-Big/Little Endian
PBL-Programmable Burst Length
0
DSL-Descriptor Skip Length
BAR-Bus Arbitration
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MX98726 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE |
| MX98726AEC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| MX98726EC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE |
| MX98727 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| MX98728 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
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