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參數(shù)資料
| 型號： | MX98725 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE CHIP FAST ETHERNET NIC CONTROLLER |
| 中文描述： | 單晶片快速以太網(wǎng)卡控制器 |
| 文件頁數(shù)： | 15/33頁 |
| 文件大?。?/td> | 177K |
| 代理商： | MX98725 |
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15
P/N:PM0488
REV. 1.7, SEP. 15, 1998
MX98725
Field
10
Name
ETI
Description
Early Transmit Interrupt, indicating the packet to be transmitted was fully transferred to
internal TX FIFO. CSR5<0> will automatically clears this bit.
Receive Watchdog Timeout, reflects the network line status where receive watchdog
timer has expired while the other node is still active on the network.
Write only, when written with any value, MX98725 reads receive descriptor list in host
memory pointed by CSR4 and processes the list.
Receive Buffer Unavailable, the receive process is suspended due to the next descriptor
in the receive list is owned by host. If no receive poll command is issued, the reception
process resumes when the next recognized incoming frame is received.
Receive Interrupt, indicating the completion of a frame reception.
Transmit Underflow, indicating transmit FIFO has run empty before the completion of a
packet transmission.
When autonegotiation is not enabled ( CSR14<7>=0 ), this bit indicates that the 10Base-
T link integrity test has completed successfully, after the link was down. This bit is also set
as as a result of writing 0 to CSR14<12> ( Link Test Enable ).
When Autonegotiation is enabled ( CSR14<7> =1 ) , this bit indicates that the autonegotiation
has completed ( CSR12<14:12>=5 ). CSR12 should then be read for a link status report.
This bit is only valid when CSR6<18>=0, i.e. 10 Base-T port is selected Link Fail interrupt
( CSR5<12> ) will automatically clears this bit.
Transmit Jabber Timeout, indicating the MX98725 has been excessively active. The
transmit process is aborted and placed in the stopped state. TDES0<1> is also set.
Transmit Buffer Unavailable, transmit process is suspended due to the next descriptor in
the transmit list is owned by host.
Transmit Process Stopped.
Transmit Interrupt. indicating a frame transmission was completed.
9
RWT
8
RPS
7
RU
6
5
RI
UNF
4
LPANCI
3
TJT
2
TU
1
0
TPS
TI
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| MX98905BFC | The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MX98726 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE |
| MX98726AEC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| MX98726EC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE |
| MX98727 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| MX98728 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
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