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參數(shù)資料
| 型號(hào)： | MX98725 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE CHIP FAST ETHERNET NIC CONTROLLER |
| 中文描述： | 單晶片快速以太網(wǎng)卡控制器 |
| 文件頁(yè)數(shù)： | 11/33頁(yè) |
| 文件大?。?/td> | 177K |
| 代理商： | MX98725 |
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11
P/N:PM0488
REV. 1.7, SEP. 15, 1998
MX98725
5.2 HOST INTERFACE REGISTERS
MX98725 CSRs are located in the host I/O or memory address space. The CSRs are double word aligned and 32
bits long. Definitions and address for all CSRs are as follows :
CSR Mapping
Register
Meaning
Offset from CSR Base
Address ( PBIO and PBMA )
00h
08h
10h
18h
20h
28h
30h
38h
40h
48h
50h
58h
60h
68h
70h
78h
80h
A0h
CSR0
CSR1
CSR2
CSR3
CSR4
CSR5
CSR6
CSR7
CSR8
CSR9
CSR10
CSR11
CSR12
CSR13
CSR14
CSR15
CSR16
CSR20
Bus mode
Transmit poll demand
Receive poll demand
Receive list demand
Transmit list base address
Interrupt status
Operation mode
Interrupt enable
Missed frame counter
Serial ROM and MII management
Reserved
General Purpose timer
10 Base-T status port
SIA Reset Register
10 Base-T control port
Watchdog timer
Magic Packet Register
NWay Status Register
bit 1-0 : Power_State, read/write.
bit7-2 : all 0. Reserved.
bit8 : PME_EN, set 1 to enable PMEB. Set 0 to disable PMEB assertion.
bit 12-9 : Data_Select for report in the Data register located at bit 31:24.
bit 14-13 : Data_Scale, read only.
bit 15 : PME_Status independent of the state of PME_EN.
When set, indicates a assertion of PMEB pin. (support D3 cold).
Write 1 to clear the PMEB signal. Write 0, no effect.
bit 21-16 : Reserved.
bit 22 : B2_B3#, B2_B3 support for D3 hot, meaningful only if BPCC_EN = 1, read only.
bit 23 : BPCC_EN, Bus Power/Clock Control Enable, read only.
bit 31-24 : Data, read only.
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| MX98726 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE |
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| MX98727 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| MX98728 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
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