參數(shù)資料
型號(hào): MX98725
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE CHIP FAST ETHERNET NIC CONTROLLER
中文描述: 單晶片快速以太網(wǎng)卡控制器
文件頁(yè)數(shù): 14/33頁(yè)
文件大小: 177K
代理商: MX98725
14
P/N:PM0488
REV. 1.7, SEP. 15, 1998
MX98725
5.2.5 STATUS REGISTER ( CSR5 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RS-Receive Process State
NIS-Normal Interrupt Summary
AIS-Abnormal Interrupt Summary
ERI-Early Receive Interrupt
FBE-Fatal Bus Error
LF-Link Fail
ETI-Early Transmit Interrupt
RWT-Receive Watchdog Timeout
GTE-General Purpose Timer Expired
MPI-Magic Packet Interrupt
LC-Link Change
RPS-Receive Process Stopped
RU-Receive Buffer Unavailable
RI-Receive Interrupt
EB-Error Bits
TS-Transmit Process State
LPACI-Link Pass/Autonegotiation
Completed Interrupt
UNF-Transmit Underflow
TJT-Transmit Jabber Timeout
TU-Transmit Buffer Unavailable
TPS-Transmit Process Stopped
TI-Transmit Interrupt
Field
28
27
Name
MPI
LC
Description
Magic packet received interrupt. Valid only if CSR16<22> bit is set.
100 Base-TX link status has changed either from pass to fail or fail to pass.
Read CSR12<1> for 100 Base-TX link status.
Error Bits, read only, indicating the type of error that casued fatal bus error.
Transmit Process State, read only bits indicating the state of transmit
Receive Process State, read only bits indicating the state of receive process.
Normal Interrupt Summary, is the logical OR of CSR5<0>, CSR5<2> and CSR5<6> and
CSR5<28>.
Abnormal Interrupt Summary, is the logical OR of CSR5<1>, CSR5<3>, CSR5<5>,
CSR5<7>, CSR5<8>, CSR5<9>, CAR5,10>, CSR5<11> and CSR5<13>, CSR5<27>.
Early receive interrupt, indicating the first buffer has been filled in ring mode, or 64 bytes
has been received in chain mode.
Fatal Bus Error, indicating a system error occured, MX98725 will disable all bus access.
Link Fail, indicates a link fail state in 10 Base-T port. This bit is valid only when CSR6<18>=0,
CSR14<8>=1, and CSR13<3>=0.
General Purpose Timer Expired, indicating CSR11 counter has expired.
25:23
22:20
19:17
16
EB
TS
RS
NIS
process.
15
AIS
14
ERI
13
12
FBE
LF
11
GTE
相關(guān)PDF資料
PDF描述
MX98905B The MX98905 is designed for easy implementation of CSMA/CD local area networks,
MX98905B IEEE 802.3, 10BASE5, 10BASE2 Controller and Integrated Bus Interface(IEEE 802.3, 10BASE5, 10BASE2控制器和集成總線接口)
MX98905BFC The MX98905 is designed for easy implementation of CSMA/CD local area networks,
MXA2312A Low Cost, +2,-2 g Dual Axis Accelerometer with Analog Outputs
MXA2500K Ultra Low Cost, 【1.0 g Dual Axis Accelerometer with Absolute Outputs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MX98726 制造商:MCNIX 制造商全稱:Macronix International 功能描述:SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE
MX98726AEC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference
MX98726EC 制造商:MCNIX 制造商全稱:Macronix International 功能描述:SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE
MX98727 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER
MX98728 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION