參數(shù)資料
型號(hào): MX98725
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE CHIP FAST ETHERNET NIC CONTROLLER
中文描述: 單晶片快速以太網(wǎng)卡控制器
文件頁(yè)數(shù): 8/33頁(yè)
文件大?。?/td> 177K
代理商: MX98725
8
P/N:PM0488
REV. 1.7, SEP. 15, 1998
MX98725
5.1.5 PCI BASE MEMORY ADDRESS REGISTER ( PBMA ) ( Offset 17h-14h )
5.1.6 PCI SUBSYSTEM ID REGISTER ( PSID ) ( Offset 2Ch-2Fh )
5.1.7 PCI BASE EXPANSION ROM ADDRESS REGISTER ( PBER ) ( Offset 33h-30h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Configuration Base Memory Address
Memory Spec Indicator
bit 0 : Memory Space Indicator, fixed to 0 in this field will map into the memory space. This is a read only field.
bit 6 - 1 : not used, all 0 when read
bit 31 - 7 : Defines the address assignment mapping of MX98725 CSR registers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Subsystem ID (31:16)
Subsystem Vendor ID (bit 15:0)
This register is used to uniquely identify the add-on board or subsystem where the NIC controller resides. Values in
this register are loaded directly from external serial EEPROM after system reset automatically. Word location 36h of
EEPROM is subsystem vendor ID and location 35h is sub-system ID.
bit 0 : Address Decode Enable, decoding will be enabled if only both enable bit in PFCS<1> and this expansion ROM
register are 1.
bit 10 - 1 : not use
bit 31 - 11 : Defines the upper 21 bits of expansion ROM base address.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Expansion ROM Base Address (upper 21 bit)
Address Decode Enable
0 0 0 0 0 0 0
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