參數(shù)資料
型號(hào)： MTV412M
廠商： Electronic Theatre Controls, Inc.
英文描述： PT 2C 2#20 PIN PLUG
中文描述： 8051嵌入式控制器的ISP監(jiān)控128K閃存式
文件頁(yè)數(shù)： 19/26頁(yè)
文件大?。?/td> 255K
代理商： MTV412M
MYSON-CENTURY
TECHNOLOGY
MTV412M
(Rev 0.9)
SLVA1ADR
(w) : Slave IIC block A1's enable and address.
EnslvA1= 1
→
Enables slave IIC block A1.
= 0
→
Disables slave IIC block A1.
bit6-0 :
Slave IIC address A1 to which the slave block should respond.
RCBBUF
(r) : Slave IIC block B receives data buffer.
TXBBUF
(w) : Slave IIC block B transmits data buffer.
SLVBADR
(w) : Slave IIC block B's enable and address.
ENslvB = 1
→
Enables slave IIC block B.
= 0
→
Disables slave IIC block B.
bit6-0 :
Slave IIC address B to which the slave block should respond.
DDCCTRA2
(w) : DDC interface control register for HSCL2, HSDA2 pins.
DDC1en = 1
→
Enables DDC1 data transfer in DDC1 mode.
= 0
→
Disables DDC1 data transfer in DDC1 mode.
En128W = 1
→
The lower 128 bytes (00-7F) of DDCRAM2 can be written by IIC master.
= 0
→
The lower 128 bytes (00-7F) of DDCRAM2 cannot be written by IIC master.
En256W = 1
→
The higher 128 bytes (80-FF) of DDCRAM2 can be written by IIC master.
= 0
→
The higher 128 bytes (80-FF) of DDCRAM2 cannot be written by IIC master.
Only128 = 1
→
The SlaveA2 always accesses EDID data from the lower 128 bytes of DDCRAM2.
= 0
→
The SlaveA2 accesses EDID data from the whole 256 bytes DDCRAM2.
SlvA2bs1,SlvA2bs0 : Slave IIC block A2's slave address length.
= 1,0
→
5-bit slave address.
= 0,1
→
6-bit slave address.
= 0,0
→
7-bit slave address.
SLVA2ADR
(w) : Slave IIC block A2's enable and address.
EnslvA2= 1
→
Enables slave IIC block A2.
= 0
→
Disables slave IIC block A2.
bit6-0 :
Slave IIC address A2 to which the slave block should respond.
8. Low Power Reset (LVR) & Watchdog Timer
When the voltage level of power supply is below 3.8V(+/-0.2V) / 2.5V(+/-0.15V) in 5V / 3.3V applications for
a specific period of time, the LVR generates a chip reset signal. After the power supply is above 3.8V(+/-
0.2V) / 2.5V(+/-0.15V) in 5V / 3.3V applications, LVR maintains in reset state for 144 X'tal cycle to guarantee
the chip exit reset condition with a stable X'tal oscillation.
The Watchdog Timer automatically generates a device reset when it is overflowed. The interval of overflow
is 0.25 sec x N, where N is a number from 1 to 8, and can be programmed via register WDT(2:0). The timer
function is disabled after power on reset, users can activate this function by setting WEN, and clear the timer
by setting WCLR.
9. A/D converter
The MTV312M is equipped with four VDD range 8-bit A/D converters. So if the VDD = 5V/3.3V, and then the
ADC conversion range is 5V/3.3V, S/W can select the current convert channel by setting the SADC1/SADC0
bit. The refresh rate for the ADC is OSC freq./1536 (128us for 12MHz X'tal).
Revision 0.9 - 19 - April 2002
= 1,0
= 0,1
= 0,0
→
5-bit slave address.
→
6-bit slave address.
→
7-bit slave address.
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