參數(shù)資料
型號(hào)： MTV412M
廠商： Electronic Theatre Controls, Inc.
英文描述： PT 2C 2#20 PIN PLUG
中文描述： 8051嵌入式控制器的ISP監(jiān)控128K閃存式
文件頁(yè)數(shù)： 11/26頁(yè)
文件大小： 255K
代理商： MTV412M
MYSON-CENTURY
TECHNOLOGY
MTV412M
(Rev 0.9)
Revision 0.9 - 11 - April 2002
6.1 Composite SYNC separation/insertion
The MTV412M continuously monitors the input HSYNC. If the vertical SYNC pulse can be extracted from
the input, a CVpre flag is set and users can select the extracted "CVSYNC" for the source of polarity check,
frequency count, and VBLANK output. The CVSYNC then has 8us delay compared to the original signal.
The MTV412M can also insert pulse to HBLANK output during composite VSYNC’s active time. The width of
insert pulse is 1/8 HSYNC period and the insertion frequency can adapt to original HSYNC. The insert pulse
of HBLANK can be disabled or enabled by setting “NoHins” control bit. If “NoHins” bit is set to "1", HBLANK
output will be same as HSYNC input (of course, polarity can be controlled by HBpl bit).
6.2 H/V Frequency Counter
MTV412M can discriminate HSYNC/VSYNC frequency and save the information in XFRs. The 14-bit
Hcounter counts the time of 64xHSYNC period, then loads the result into the HCNTH/HCNTL latch. The
output value is then [(128000000/H-Freq) - 1], updated once per VSYNC/CVSYNC period when
VSYNC/CVSYNC is present or continuously updated when VSYNC/CVSYNC is non-present. The 12-bit
Vcounter counts the time between two VSYNC pulses, then loads the result into the VCNTH/VCNTL latch.
The output value is then (62500/V-Freq), updated every VSYNC/CVSYNC period. An extra overflow bit
indicates the condition of H/V counter overflow. The VFchg/HFchg interrupt is set when VCNT/HCNT value
changes or overflows. Table 6.2.1 and Table 6.2.2 show the HCNT/VCNT value under the operations of
12MHz.
Hpol
CVpre
Vbpl
VSYNC
Digital Filter
Polarity Check &
Sync Seperator
Vpre
Present
Check
Vfreq
Vpol
Polarity Check &
Freq. Count
XOR
VBLANK
Vself
XOR
HSYNC
Digital Filter
CVSYNC
Present
Check
Hpre
Hfreq
Present Check &
Freq. Count
XOR
Hbpl
XOR
HBLANK
Composite
Pulse Insert
H/V SYNC Processor Block Diagram
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