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參數(shù)資料
| 型號： | MTV412M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PT 2C 2#20 PIN PLUG |
| 中文描述： | 8051嵌入式控制器的ISP監(jiān)控128K閃存式 |
| 文件頁數(shù)： | 13/26頁 |
| 文件大?。?/td> | 255K |
| 代理商： | MTV412M |
MYSON-CENTURY
TECHNOLOGY
MTV412M
(Rev 0.9)
Revision 0.9 - 13 - April 2002
6.2.1 H-Freq Table
Output Value (14 bits)
12MHz OSC (hex / dec)
0FDEh / 4062
0D54h / 3412
0B8Bh / 2955
0AA8h / 2728
094Fh / 2383
0854h / 2132
0746h / 1862
06AAh / 1706
063Fh / 1599
05D1h / 1489
0554h / 1364
04B3h / 1203
H-Freq(KHZ)
1
2
3
4
5
6
7
8
9
10
11
12
31.5
37.5
43.3
46.9
53.7
60.0
68.7
75.0
80.0
85.9
93.8
106.3
6.2.2 V-Freq Table
Output value (12bits)
12MHz OSC (hex / dec)
45Ch / 1116
411h / 1041
37Ch / 892
364h / 868
341h / 833
2DFh / 735
V-Freq(Hz)
1
2
3
4
5
6
56
60
70
72
75
85
6.3 H/V Present Check
The Hpresent function checks the input HSYNC pulse, and the Hpre flag is set when HSYNC is over 10KHz
or cleared when HSYNC is under 10Hz. The Vpresent function checks the input VSYNC pulse, and the Vpre
flag is set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz. The HPRchg interrupt is set
when the Hpre value changes. The VPRchg interrupt is set when the Vpre/CVpre value change.
6.4 H/V Polarity Detect
The polarity functions detect the input HSYNC/VSYNC high and low pulse duty cycle. If the high pulse
duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is
asserted. The HPLchg interrupt is set when the Hpol value changes. The VPLchg interrupt is set when the
Vpol value changes.
6.5 Output HBLANK/VBLANK Control and Polarity Adjust
The HBLANK is the mux output of HSYNC and composite Hpulse. The VBLANK is the mux output of
VSYNC and CVSYNC. The mux selection and output polarity are S/W controllable. The VBLANK output is
cut off when VSYNC frequency is over 250Hz. The HBLANK/VBLANK shares the output pin with P4.1/ P4.0.
6.6 VSYNC Coast Pulse Output
This output pin define the period of ADC PLL which is needed to disable locking for composite sync. The
output polarity of VCOAST are S/W controllable.
6.7 HSYNC Clamp Pulse Output
The HCLAMP output is activated by setting “HCLPE” control bit. The leading edge position, pulse width and
polarity of HCLAMP are S/W controllable.
6.8 VSYNC Interrupt
The MTV412M checks the VSYNC input pulse and generates an interrupt at its leading edge. The VSYNC
flag is set each time when MTV412M detects a VSYNC pulse. he flag is cleared by S/W writing a "0".
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相關(guān)代理商/技術(shù)參數(shù) |
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| MTV412MS128 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8051 Embedded Monitor Controller 128K Flash Type with ISP |
| MTV412MV128 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8051 Embedded Monitor Controller 128K Flash Type with ISP |
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