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| 型號： | MTV412M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PT 2C 2#20 PIN PLUG |
| 中文描述： | 8051嵌入式控制器的ISP監(jiān)控128K閃存式 |
| 文件頁數(shù)： | 16/26頁 |
| 文件大?。?/td> | 255K |
| 代理商： | MTV412M |
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MYSON-CENTURY
TECHNOLOGY
MTV412M
(Rev 0.9)
7. DDC & IIC Interface
7.1 DDC1/DDC2x Mode, DDCRAM1/DDCRAM2 and SlaveA1/SlaveA2 block
The MTV412M supports VESA DDC for both D-sub and DVI interfaces through HSCL1/HSDA1 and
HSCL2/HSDA2 pins. The HSCL1/HSDA1 pins access DDCRAM1 by SlaveA1, and the HSCL2/HSDA2 pins
access DDCRAM2 by SlaveA2. The MTV412M enters DDC1 mode for both DDC channels after Reset. In
this mode, VSYNC is used as data clock. The HSCL1/HSCL2 pin should remain at high. The data output to
the HSDA1/HSDA2 pin is taken from a shift register in MTV412M. The shift register automatically fetches
EDID data from the lower 128 bytes of the Dual Port RAM (DDCRAM1/DDCRAM2), then sends it in 9-bit
packet formats inclusive of a null bit (=1) as packet separator. S/W may enable/disable the DDC1 function
by setting/clearing the DDC1en control bit.
The MTV412M switches to DDC2x mode when it detects a high to low transition on the HSCL1/HSCL2 pin.
In this mode, the SlaveA1/SlaveA2 IIC block automatically transmits/receives data to/from the IIC Master.
The transmitted/received data is taken-from/saved-to the DDCRAM1/DDCRAM2. In simple words,
MTV412M can behaves as two 24LC02 EEPROMs. The only thing S/W needs to do is to write the EDID
data to DDCRAM1/DDCRAM2. These slave address of SlaveA1/SlaveA2 block can be chosen by S/W as 5-
bit, 6-bit or 7-bit. For example, if S/W chooses 5-bit slave address as 10100b, the SlaveA1 IIC block then
responds to slave address 10100xxb. The SlaveA1/SlaveA2 can be enabled/disabled by setting/clearing the
EnslvA1/EnslvA2 bit. The lower/upper DDCRAM1/DDCRAM2 can/cannot be written by the IIC Master by
setting/clearing the EN128w/En256w bit. Besides, if the Only128 control bit is set, the SlaveA1/SlaveA2 only
accesses the lower 128 bytes of the DDCRAM1/DDCRAM2.
The MTV412M returns to DDC1 mode if HSCL1 is kept high for 128 VSYNC clock period. However, it locks
in DDC2B mode if a valid IIC address (1010xxxb) has been detected on HSCL1/HSDA1 buses. The DDC2
flag reflects the current DDC status, S/W may clear it by writing a "0" to it.
7.2 SlaveB Block
The SlaveB IIC block is connected to HSDA1 and HSCL1 pins only. This block can receive/transmit data
using IIC protocols. S/W may write the SLVBADR register to determine the slave addresses.
In receive mode, the block first detects IIC slave address matching the condition then issues a SlvBMI
interrupt. The data from HSDA1 is shifted into shift register then written to RCBBUF register when a data
byte is received. The first byte loaded is word address (slave address is dropped). This block also generates
a RCBI (receives buffer full interrupt) every time when the RCBBUF is loaded. If S/W is not able to read out
the RCBBUF in time, the next byte in shift register is not written to RCBBUF and the slave block returns
NACK to the master. This feature guarantees the data integrity of communication. The WadrB flag can tell
S/W whether the data in RCBBUF is a word address or not.
In transmit mode, the block first detects IIC slave address matching the condition, then issues a SlvBMI
interrupt. In the meantime, the data pre-stored in the TXBBUF is loaded into shift register, resulting in
TXBBUF emptying and generates a TXBI (transmit buffer empty interrupt). S/W should write the TXBBUF a
new byte for the next transfer before shift register empties. A failure of this process causes data corrupt. The
TXBI occurs every time when shift register reads out the data from TXBBUF.
The SlvBMI is cleared by writing "0" to corresponding bit in INTFLG register. The RCBI is cleared by reading
out RCBBUF. The TXBI is cleared by writing TXBBUF.
*Please refer to the attachments about "Slave IIC Block Timing".
7.3 Master Mode IIC Function Block
The master mode IIC block can be connected to the ISDA /ISCL pins or the HSDA1/HSCL1 pins, selected by
Msel control bit. Its speed can be selected within the range of 50KHz-400KHz by S/W setting the
MIICF1/MIICF0 control bit. The software program can access the external IIC device through this interface. A
summary of master IIC access is illustrated as follows.
Revision 0.9 - 16 - April 2002
EVF
EVsync = 1
= 1
→
Enables VSYNC frequency change / counter overflow interrupt.
→
Enables VSYNC interrupt.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MTV412MF128 | 8051 Embedded Monitor Controller 128K Flash Type with ISP |
| MTV412MS128 | 8051 Embedded Monitor Controller 128K Flash Type with ISP |
| MTV412MV128 | 8051 Embedded Monitor Controller 128K Flash Type with ISP |
| MU93-4001 | SUPER BRIGHT LED LIGHT BAR MODULE |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MTV412MF128 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8051 Embedded Monitor Controller 128K Flash Type with ISP |
| MTV412MS128 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8051 Embedded Monitor Controller 128K Flash Type with ISP |
| MTV412MV128 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8051 Embedded Monitor Controller 128K Flash Type with ISP |
| MTV-50 | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:Two-Way Power Dividers, 1 - 100 MHz and 40 - 400 MHz |
| MTV50CD35 | 制造商:Mallory Sonalert Products Inc 功能描述:Molded Case Vertical-Mount Electrolytic Radial Leads Capacitor - 50uF 35dcV -10+100% |
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