參數(shù)資料
型號(hào)： MTV412M
廠商： Electronic Theatre Controls, Inc.
英文描述： PT 2C 2#20 PIN PLUG
中文描述： 8051嵌入式控制器的ISP監(jiān)控128K閃存式
文件頁數(shù)： 17/26頁
文件大?。?/td> 255K
代理商： MTV412M
MYSON-CENTURY
TECHNOLOGY
MTV412M
(Rev 0.9)
7.3.1. To write IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV412M transmits this byte, a MbufI interrupt is triggered.
4. Programs can write MBUF to transfer next byte or set P bit to stop.
* Please refer to the attachments about "Master IIC Transmit Timing".
7.3.2. To read IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV412M transmits this byte, a MbufI interrupt is triggered.
4. Set or reset the MAckO flag according to the IIC protocol.
5. Read out MBUF the useless byte to continue the data transfer.
6. After the MTV412M receives a new byte, the MbufI interrupt is triggered again.
7. Read MBUF also trigger the next receive operation, but set P bit before read can terminate the operation.
* Please refer to the attachments about "Master IIC Receive Timing".
Reg name
addr
bit7
bit6
bit5
IICCTR
F00h (r/w) DDC2A1 DDC2A2
IICSTUS
F01h (r)
WadrB
SlvRWB SAckIn
INTFLG
F03h (r)
TXBI
RCBI
SlvBMI
INTFLG
F03h (w)
SlvBMI
INTEN
F04h (w)
ETXBI
ERCBI ESlvBMI ESTOPI EReStaI EWSlvA1I EWSlvA2I EMbufI
MBUF
F05h (r/w)
Master IIC receive/transmit data buffer
DDCCTRA1
F06h (w) DDC1en En128W En256W Only128
SLVA1ADR
F07h (w) ENSlvA1
RCBBUF
F08h (r)
Slave B IIC receive buffer
TXBBUF
F08h (w)
Slave B IIC transmit buffer
SLVBADR
F09h (w) ENSlvB
DDCCTRA2
F86h (w) DDC1en En128W En256W Only128
SLVA2ADR
F87h (w) ENSlvA2
IICCTR
(r/w) : IIC interface status/control register.
DDC2A1 = 1
→
DDC2 is active for HSCL1/HSDA1 pins.
= 0
→
MTV412M remains in DDC1 mode for HSCL1/HSDA1 pins.
DDC2A2 = 1
→
DDC2 is active for HSCL2/HSDA2 pins.
= 0
→
MTV412M remains in DDC1 mode for HSCL2/HSDA2 pins.
MAckO = 1
→
In master receive mode, NACK is returned by MTV412M.
= 0
→
In master receive mode, ACK is returned by MTV412M.
S, P
=
↑
, 0
→
Start condition when Master IIC is not during transfer.
= X,
↑
→
Stop condition when Master IIC is not during transfer.
= 1, X
→
Resume transfer after a read/write MBUF operation.
IICSTUS
(r) : IIC interface status register.
WadrB = 1
→
The data in RCBBUF is word address.
SlvRWB = 1
→
Current transfer is slave transmit
= 0
→
Current transfer is slave receive
SAckIn = 1
→
The external IIC host respond NACK.
SLVS = 1
→
The slave block has detected a START, cleared when STOP detected.
MAckIn = 1
→
Master IIC bus error, no ACK received from the slave IIC device.
= 0
→
ACK received from the slave IIC device.
Revision 0.9 - 17 - April 2002
bit4
bit3
SLVS
ReStaI
ReStaI
bit2
MAckO
WslvA1I WslvA2I
WslvA1I WslvA2I
bit1
P
bit0
S
MAckIn
MbufI
MbufI
STOPI
STOPI
SlvA1bs1 SlvA1bs0
Slave A1 IIC address
Slave B IIC address
Slave A2 IIC address
SlvA2bs1 SlvA2bs0
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