參數(shù)資料
型號(hào): MT93L04
廠商: Zarlink Semiconductor Inc.
英文描述: 128-Channel Voice Echo Canceller
中文描述: 128頻道語音回聲消除器
文件頁數(shù): 5/56頁
文件大?。?/td> 903K
代理商: MT93L04
MT93L04
Data Sheet
5
Zarlink Semiconductor Inc.
IRQB_d1
User Signal
J5
Interrupt Request (Open Drain Output).
This
output goes low when an interrupt occurs in any
channel. IRQ returns high when all the interrupts
have been read from the Interrupt FIFO Register.
A pull-up resistor (1 K typical) is required at this
output.
DSB_d1
User Signal
H2
Data Strobe (Input).
This active low input works
in conjunction with CS to enable the read and
write operations.
CSB_d1
User Signal
K3
Chip Select (Input).
This active low input is used
by a microprocessor to activate the
microprocessor port.
R/WB_d1
User Signal
H3
Read/Write (Input).
This input controls the
direction of the data bus lines (D7-D0) during a
microprocessor access.
DTAB_d1
User Signal
K4
Data Transfer Acknowledgment (Open Drain
Output).
This active low output indicates that a
data bus transfer is completed. A pull-up resistor
(1 K typical) is required at this output.
D(0)_d1
User Signal
H4
Data Bus D0 - D7 (Bidirectional).
These pins
form the 8-bit bidirectional data bus of the
microprocessor port.
D(1)_d1
User Signal
K5
D(2)_d1
User Signal
H5
D(3)_d1
User Signal
G4
D(4)_d1
User Signal
G5
D(5)_d1
User Signal
F4
D(6)_d1
User Signal
F5
D(7)_d1
User Signal
E5
A(0)_d1
User Signal
D4
Address A0 to A10 (Input).
These inputs provide
the A10 - A0 address lines to the internal
registers.
A(1)_d1
User Signal
E6
A(2)_d1
User Signal
D5
A(3)_d1
User Signal
E7
A(4)_d1
User Signal
D7
A(5)_d1
User Signal
E8
A(6)_d1
User Signal
E10
A(7)_d1
User Signal
D8
A(8)_d1
User Signal
D10
A(9)_d1
User Signal
C10
A(10)_d1
User Signal
B10
Pin Description (continued)
Signal Name
Signal Type
BGA Ball #
Signal Description
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MT93L04A 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:128-Channel Voice Echo Canceller
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