參數(shù)資料
型號: MT93L04
廠商: Zarlink Semiconductor Inc.
英文描述: 128-Channel Voice Echo Canceller
中文描述: 128頻道語音回聲消除器
文件頁數(shù): 12/56頁
文件大小: 903K
代理商: MT93L04
MT93L04
Data Sheet
12
Zarlink Semiconductor Inc.
Tsig(11)_d2
NC
R1
No connection.
The pin must be left open for
normal operation.
Tsig(12)_d2
NC
R2
No connection.
The pin must be left open for
normal operation.
Tsig(13)_d2
NC
P3
No connection.
The pin must be left open for
normal operation.
Tsig(14)_d2
NC
T1
No connection.
The pin must be left open for
normal operation.
Tsig(15)_d2
NC
U1
No connection.
The pin must be left open for
normal operation.
Tm1_d2
ICO
T2
Internal Connection.
Connected to VSS for
normal operation
Tm2_d2
ICO
R3
Internal Connection.
Connected to VSS for
normal operation
Sg1_d2
ICO
R4
Internal Connection.
Connected to VSS for
normal operation
DT1_d2
NC
V1
No connection.
The pin must be left open for
normal operation.
MCLK_d2
Signal
U2
Master Clock (Input).
Nominal 10 MHz or
20 MHz Master Clock input. May be connected to
an asynchronous (relative to frame signal) clock
source.
Fsel_d2
Signal
W1
Frequency select (Input).
This input selects the
Master Clock frequency operation. When Fsel pin
is low, nominal 19.2 MHz Master Clock input must
be applied. When Fsel pin is high, nominal
9.6 MHz Master Clock input must be applied.
Halt_d2
ICO
T3
Internal Connection.
Connected to VSS for
normal operation
Step_d2
ICO
V2
I
nternal Connection.
Connected to VSS for
normal operation
PLLVSS1_d2
Power
Y1
PLL Ground.
Must be connected to VSS
PLLVDD_d2
Power
W2
PLL Power Supply
. Must be connected to VDD2
PLLVSS2_d2
Power
U3
PLL Ground.
Must be connected to VSS
AT1_d2
NC
V3
No connection.
The pin must be left open for
normal operation.
DEVICE 3
TMS_d3
Signal
W13
Test Mode Select (3.3 V Input).
JTAG signal that
controls the state transitions of the TAP controller.
This pin is pulled high by an internal pull-up when
not driven.
Pin Description (continued)
Signal Name
Signal Type
BGA Ball #
Signal Description
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