參數(shù)資料
型號(hào)： MT9300BV
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 數(shù)字傳輸電路
英文描述： Multi-Channel Voice Echo Canceller
中文描述： DATACOM, ISDN ECHO CANCELLER, PBGA208
封裝： 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208
文件頁(yè)數(shù)： 8/39頁(yè)
文件大小： 629K
代理商： MT9300BV
MT9300B
Data Sheet
8
Zarlink Semiconductor Inc.
Device Overview
The MT9300B architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo
cancellers, Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or
Back-to-Back configurations. In
Normal configuration
, a group of echo cancellers provides two channels of 64ms
echo cancellation, which run independently on different channels. In
Extended Delay
configuration, a group of
echo cancellers achieves 128ms of echo cancellation by cascading the two echo cancellers (A & B). In
Back-to-
Back
configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both
directions in a single channel, providing full-duplex 64ms echo cancellation.
Each echo canceller contains the following main elements (see Figure 4).
Adaptive Filter for estimating the echo channel
Subtractor for cancelling the echo
Double-Talk detector for disabling the filter adaptation during periods of double-talk
Path Change detector for fast reconvergence on major echo path changes
Instability Detector to combat oscillation in very low ERL environments
Non-Linear Processor for suppression of residual echo
Disable Tone Detectors for detecting valid disable tones at send and receive path inputs
Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals
Offset Null filters for removing the DC component in PCM channels
12dB attenuator for signal attenuation
Parallel controller interface compatible with Motorola microcontrollers
PCM encoder/decoder
compatible with
μ
/A-Law ITU-T G.711 or Sign-Magnitude coding
Each echo canceller in the MT9300B has four functional states:
Mute
,
Bypass
,
Disable Adaptation
and
Enable
Adaptation
. These are explained in the section entitled Echo Canceller Functional States.
Figure 4 - Echo Canceller Functional Block Diagram
Linear/
μ
/A-Law
+
Non-Linear
Processor
Offset
Null
μ
/A-Law/
Linear
Linear/
μ
/A-Law
Microprocessor
Interface
Double-Talk
Detector
Disable Tone
Detector
A
F
C
Narrow-Band
Detector
μ
/A-Law/
Linear
Offset
Null
Echo Canceller (N), where 0
≤
N
≤
31
Sout
Sin
Rout
-
Programmable
Bypass
Disable Tone
Detector
(channel N)
(channel N)
(channel N)
(chaRin
GCI
PORT1
GCI
PORT2
12dB
Attenuator
MuteR
MuteS
Instability
Detector
Path Change
Detector
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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