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參數(shù)資料
| 型號： | MT9300BV |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Multi-Channel Voice Echo Canceller |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
| 封裝： | 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208 |
| 文件頁數(shù)： | 7/39頁 |
| 文件大?。?/td> | 629K |
| 代理商： | MT9300BV |
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MT9300B
Data Sheet
7
Zarlink Semiconductor Inc.
A4
112
C4i
Serial Clock (Input).
4.096 MHz serial clock for shifting
data in/out on the serial streams (Rin, Sin, Rout, Sout).
G2
140
MCLK
Master Clock (Input).
Nominal 10 MHz or 20 MHz Master
Clock input. May be connected to an asynchronous
(relative to frame signal) clock source.
H2
143
Fsel
Frequency select (Input).
This input selects the Master
Clock frequency operation. When Fsel pin is low, nominal
19.2 MHz Master Clock input must be applied. When Fsel
pin is high, nominal 9.6 MHz Master Clock input must be
applied.
K3
146
PLLV
SS
PLL Ground.
Must be connected to V
SS
.
PLLV
DD
PLL Power Supply.
Must be connected to V
DD1
.
TMS
Test Mode Select (3.3 V Input).
JTAG signal that controls
the state transitions of the TAP controller. This pin is pulled
high by an internal pull-up when not driven.
K4
147
M2
152
M1
153
TDI
Test Serial Data In (3.3 V Input).
JTAG serial test
instructions and data are shifted in on this pin. This pin is
pulled high by an internal pull-up when not driven.
N1
154
TDO
Test Serial Data Out (Output).
JTAG serial data is output
on this pin on the falling edge of TCK. This pin is held in
high impedance state when JTAG scan is not enabled.
P1
155
TCK
Test Clock (3.3 V Input).
Provides the clock to the JTAG
test logic.
N2
156
TRST
Test Reset (3.3 V Input).
Asynchronously initializes the
JTAG TAP controller by putting it in the Test-Logic-Reset
state. This pin should be pulsed low on power-up or held
low, to ensure that the MT9300B is in the normal functional
mode. This pin is pulled by an internal pull-down when not
driven.
R3
158
RESET
Device Reset (Schmitt Trigger Input).
An active low
resets the device and puts the MT9300B into a low-power
stand-by mode.
When the RESET pin is returned to logic high and a
clock is applied to the MCLK pin, the device will
automatically execute initialization routines, which preset
all the Control and Status Registers to their default
power-up values.
C6,D6,J3,J4,N12,P12, G13,G14
V
DD2
These LBGA pins should be wired to V
DD2
= 1.8 V for
FUTURE USE
. If the customer does not intend to use
future generation of the device, then these pins should
be NO CONNECTS
Pin Description (continued)
Pin #
Name
Description
208-Ball LBGA
160 Pin
MQFP
相關(guān)PDF資料 |
PDF描述 |
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| MT9315 | CMOS Acoustic Echo Canceller |
| MT933 | 3.3V 10/100 Fast Ethernet Transceiver to MII |
| MT933CG | 3.3V 10/100 Fast Ethernet Transceiver to MII |
| MT933TP1N | 3.3V 10/100 Fast Ethernet Transceiver to MII |
| MT93L00A | Multi-Channel Voice Echo Canceller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9315 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT933 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3.3V 10/100 Fast Ethernet Transceiver to MII |
| MT933CG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3.3V 10/100 Fast Ethernet Transceiver to MII |
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