參數(shù)資料
型號(hào): MT9300BV
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: Multi-Channel Voice Echo Canceller
中文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封裝: 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208
文件頁數(shù): 21/39頁
文件大?。?/td> 629K
代理商: MT9300BV
MT9300B
Data Sheet
21
Zarlink Semiconductor Inc.
Bit
Name
Description
7
TDis
When high, tone detection is disabled. When low, tone detection is enabled.
When both Echo Cancellers A and B TDis bits are high, Tone Disable processors are
disabled entirely and are put into power down mode.
6
PHDis
When high, the tone detectors will trigger upon the presence of a 2100 Hz tone
regardless of the presence/absence of periodic phase reversals.
When low, the tone detectors will trigger only upon the presence of a 2100 Hz tone
with periodic phase reversals.
5
NLPDis
When high, the non-linear processor is disabled.
When low, the non-linear processors function normally. Useful for G.165 conformance
testing.
4
AutoTD
When high, the echo canceller puts itself in Bypass mode when the tone detectors
detect the presence of 2100 Hz tone. See PHDis for qualification of 2100 Hz tones.
When low, the echo canceller algorithm will remain operational regardless of the state
of the 2100 Hz tone detectors.
3
NBDis
When high, the narrow-band detector is disabled. When low, the narrow-band
detector is enabled.
2
HPFDis
When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths.
When low, the offset nulling filters are active and will remove DC offsets on PCM input
signals.
1
MuteS
When high, data on Sout is muted to quiet code. When low, Sout carries active code.
0
MuteR
When high, data on Rout is muted to quiet code. When low, Rout carries active code.
Echo Canceller A, Control Register A2
Echo Canceller B, Control Register B2
MuteR
MuteS
HPFDis
NBDis
AutoTD
NLPDis
PHDis
TDis
7
6
5
4
3
2
1
0
Reset Value:
00
H
Read/Write Address:
Read/Write Address:
01
H
+ Base Address
21
H
+ Base Address
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