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參數(shù)資料
| 型號： | MT9300BV |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Multi-Channel Voice Echo Canceller |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
| 封裝： | 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208 |
| 文件頁數(shù)： | 19/39頁 |
| 文件大?。?/td> | 629K |
| 代理商： | MT9300BV |
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MT9300B
Data Sheet
19
Zarlink Semiconductor Inc.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test
operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally
pulled to V
DD
when it is not driven from an external source.
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to V
DD
when it is not driven from an external source.
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDO. The data from the TDO is clocked on
the falling edge of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO
driver is set to a high impedance state.
Test Reset (TRST)
This pin is used to reset the JTAG scan structure. This pin is internally pulled to V
SS
.
Instruction Register
In accordance with the IEEE 1149.1 standard, the MT9300B uses public instructions. The JTAG Interface contains
a 3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP
Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to
select the test data register that will operate while the instruction is current, and to define the serial test data register
path, which is used to shift data between TDI and TDO during data register scanning.
Test Data Registers
As specified in IEEE 1149.1, the MT9300B JTAG Interface contains three test data registers:
Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path
around the boundary of the MT9300B core logic.
Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI TDO.
Device Identification register
The Device Identification register provides access to the following encoded information:
device version number, part number and manufacturer's name.
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| MT933CG | 3.3V 10/100 Fast Ethernet Transceiver to MII |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT9315 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT933 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3.3V 10/100 Fast Ethernet Transceiver to MII |
| MT933CG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3.3V 10/100 Fast Ethernet Transceiver to MII |
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