參數(shù)資料
型號: MT9300BV
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: Multi-Channel Voice Echo Canceller
中文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封裝: 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208
文件頁數(shù): 32/39頁
文件大?。?/td> 629K
代理商: MT9300BV
MT9300B
Data Sheet
32
Zarlink Semiconductor Inc.
Bit
Name
Description
7
IRQ
Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt
FIFO register is read.
Logic Low indicates that no interrupt is pending and the FIFO is empty.
6:5
0
Unused bits. Always zero
4:0
I<4:0>
I<4:0> binary code indicates the channel number at which a Tone Detector state
change has occurred.
Note: Whenever a Tone Disable is detected or released, an interrupt is generated.
Bit
Name
Description
7:1
res
Reserved bits. Must always be set to zero for normal operation.
0
Tirq
Test IRQ: Useful for the application engineer to verify the interrupt service routine.
When high, any change to MTDBI and MTDAI bits of the Main Control Register will
cause an interrupt and its corresponding channel number will be available from the
Interrupt FIFO Register.
When low, normal operation is selected.
Interrupt FIFO Register
I0
I1
I2
I3
I4
0
0
IRQ
7
6
5
4
3
2
1
0
Reset Value:
00
H
Read Address:
410
H
(Read only)
Test Register
Tirq
res
res
res
res
res
res
res
7
6
5
4
3
2
1
0
Reset Value:
00
H
Read/Write Address:
411
H
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